Re: Verilog-AMS committee meeting minutes - 16 June 2011

From: Kevin Cameron <edaorg@v-ms.com>
Date: Wed Aug 31 2011 - 00:58:15 PDT

On 06/30/2011 10:06 PM, Sri Chandra wrote:
> [Apologies for the delay in sending the minutes]
>
> ....Interconnect proposal from SV-DC committee
>
> * Discussion on SV-DC proposal on user defined net types and using generic interconnect objects
> * The proposal from SV-DC as it stands today seems to be fine from the Verilog-AMS technical committee. Currently this is done in AMS through the overloading of the "wire" concept, which is not probably the right way to go about. The new proposal does not seem to break backward compatibility.
>

As it stands it reiterates a mistake made in VHDL in the 80s and Verilog-AMS (as revised by Cadence ~ '96) in using port-connections as a place to do type-conversion. But hey, at least they are all consistently wrong now.

> * Discussions around wreal and its connection mechanism to wire?
> * How does the current usage of discipline work with the user defined net types?
> o The aspect of disciplines is outside the scope of this work from SV-DC and there is no intention to look at that.
> o How will this be handled in SV-AMS integration? The AMS technical committee also feels it is not good idea to overload "electrical discipline" and prefers the usage of "interconnect" keyword that is specified in the proposal
>

> o There seems to be lack of clarity, based on discussions, on the intent of the discipline used in Verilog-AMS vs net type.
>

Gord vowed that no analog stuff would reach his simulator, perfectly clear - executing to plan.

> * The interconnect proposal is purely to specify structural connections to bridge the gap in SV where there was no structural connection available in SV before
>

That makes no sense, standard port connections are structural, at least they were when all this stuff lived at Accellera - did that change?

> * The current connectivity syntax in SV is very restrictive - only real to real connection; done on intent
> o Possibly look at removing the restrictions as we move forward with SV-AMS
>

Good luck with that. I would predict more dysfunctional semantics and unnecessary keywords myself.

Kev.

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