Call for Papers IEEE/DATC EDP 2000
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Seventh IEEE/DATC Electronic Design Processes Workshop
April 26-28, 2000
Monterey Beach Hotel, Monterey, CA
Due dates for abstracts and proposals for panels and invited speakers: to be
announced at http://www.eda.org/edps/edp00.html
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EDP will provide a forum for a cross-section of the design community to
discuss state-of-the-art electronic design processes and CAD methodologies.
Specific goals of EDP 2000 are to:
* Identify and evaluate key trends and known best practices that are
driving changes in the design process, with respect to technology and
the business model.
* Identify and evaluate the common barriers to product delivery with
respect to design processes.
* Identify and prioritize issues requiring further research in
development, deployment, and assessment of design processes and the
tools to support them.
* Review and update the "rolling roadmap" developed at earlier workshops
and disseminate findings to the design community at-large.
This 2 1/2 day workshop will include a mix of submitted presentations,
invited talks by academic professors in CAD and VLSI areas and by
engineering managers and CAD specialists from companies like Intel, Sun, and
IBM, and working group discussions.
Submissions of abstracts and suggestions for panels and invited speakers are
sought addressing both current and long term issues in all areas related to
design processes, including:
* Improving the design process
o Designer productivity
o Design turn-around time
o Design methodology repeatability and convergence
* Technology trends (deep sub-micron, high frequency)
o System level integration issues - mixed signal designs
o Managing and implementing large, dense designs
o The evolving role of the designer in very large designs
* Tool architecture and design styles
o Incremental design tool integration architectures
o Maintaining modularity of integrated incremental design tools
o Architectures for improving tool interchangeability
o Multi-source tool integration experiences
o Distributed and web-based design methodologies
o Standardization, data interchange, and interfaces for reuse of IP
* Measurement and evolution of design processes
o How to manage design process evolution
o Technology transfer for design process research
o Design process measurement techniques
o Design education, undergraduate and continuing
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Submission: Abstracts of 200-500 words in plain ASCII text. Full papers are
not required and no digest of papers will be published.
(Slides of presentations at EDP '99 can be found at
http://edp99.ece.utexas.edu/edp99.html)
Workshop David J. Hathaway Prof. Margarida F. Jacome
co-chairs: IBM Electronic University of Texas at Austin
Design Automation jacome@ece.utexas.edu
davidh@btv.ibm.com http://horizon.ece.utexas.edu/~jacome
(802) 769-6052 (512) 471-2051
Organizing Naresh Sehgal Margarida F. Jacome (U. Texas Austin)
committee: (Intel) Steve Grout (Sematech)
David Hathaway (IBM)
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Seventh IEEE/DATC Electronic Design Processes Workshop
April 26-28, 2000
Monterey Beach Hotel, Monterey, CA
Due dates for abstracts and proposals for panels and invited speakers: to be announced at http://www.ed= a.org/edps/edp00.html
Submissions of abstracts and suggestions for panels and invited speaker= s are sought addressing both current and long term issues in all areas relat= ed to design processes, including:
Submission: Abstracts of 200-500 words in plain ASCII text. Full papers are not required and no digest of papers will be published.
(Slides of presentations at EDP '99 can be found at&n=
bsp;
http://edp99.ece.utexas.edu/edp99.=
html)
| Workshop co-chairs:
|
David J. Hathaway
IBM Electronic Design Automation davidh@btv.ibm.com (802) 769-6052 |
Prof. Margarida F. Jacome
University of Texas at Austin jacome@ece.utexas.edu http://horizon.ece.u= texas.edu/~jacome (512) 471-2051 |
| Organizing committee: | Naresh Sehgal (Intel)
David Hathaway (IBM) |
Margarida F. Jacome (U. Texas Austin)
Steve Grout (Sematech) |
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