Registration to attend this free workshop is required by October 8, 1999 by
RSVP'ing to dennisb@model.com. [This workshop will be repeated in late
October in Japan. Details will be available soon.]
The development of VITAL-1999/2000, a revision to the popular VITAL-1995
standard, has been sponsored by VHDL International. This workshop will be
conducted by members of the VITAL Technical Action Group (TAG) and other
developers of the 1999/2000 version of the standard.
In the era of very deep sub-micron design where a new standards are
developing daily, VITAL is arguably one of the most successful EDA standard
with wide adoption from the design and ASIC vendor community.
The IEEE VITAL TAG under the premise of IEEE Timing Working Group is in its
final phase of drafting a new revision to this standard - VITAL-1999/2000 -
to be released later this year. The VITAL-1999/2000 standard is designed to
address various issue reports with VITAL-1995 and include significant new
modeling enhancements. The major highlights include:
o Standardized ASIC memory models
o Support of IEEE 1076-93 (VHDL93) standard
o Support of IEEE P1497 (SDF 4.0) standard
o Multi-source interconnect timing simulation
o Negative timing constraint modeling for vector signals
o SKEW timing checks
o Improvements to setup/hold timing checks
o Improvements to glitch handling
Sign-up for the workshop and learn more details about these new features.
As an added bonus, invitations from the IEEE to participate in the ballot of
VITAL-1999/2000 will be provided along with a draft copy of the
specification for review.
The new features of VITAL-1999/2000 will improve the functional, timing
accuracy significantly and aid performance of gate level VHDL simulations.
Several usability issues which have been raised with the 1995 standard have
been addressed. The VITAL TAG is currently in the process of drafting the
LRM changes for these enhancements and completing the necessary code
development to VITAL packages. Look for an IEEE Invitation to Ballot in
late September or early October to become an official member of the ballot
constituency via email.
VITAL-1999/2000 was developed with contributions from premier ASIC vendors
such as LSI Logic, Motorola, Texas Instruments, American Microsystems Inc.
and major EDA vendors such as Mentor Graphics, Model Technology, Cadence
Design Systems and Synopsys. The ASIC memory model standard is derived from
contributed work from the LSI Logic VHDL behavioral model and Mentor
Graphics Memory Table Model (MTM) techniques. The generous support of VHDL
International provided the needed funding to take these two contributed
works and convert them into the memory specification and package code by
VITAL with significant contribution coming from leading EDA services company
GDA Technologies.
You can expect detailed information on new and improved features found in
VITAL-1999/2000 including:
VITAL Memory Model
------------------
Memory devices have become an important aspect of ASIC designs. It is not
uncommon to find dozens of configurations of various memories found in a
single ASIC. Library developers have long found it relatively easy to model
memories in the Verilog HDL compared to VHDL. The VITAL TAG changes this
notion with the proposed memory modeling extensions as part of VITAL 1076.4
ASIC Modeling standard.
The main motivation to define memory modeling standards is to provide model
developers a basic infrastructure to write memory models in VHDL. This is
accomplished by defining a standard memory modeling package VITAL_Memory.
The VITAL memory package provides a method to represent memories, procedures
and functions to perform various operations such as read, write, corrupt and
the definition of a modeling style (VITAL Memory Level 1) that promotes
consistency, maintainability and tool optimization. This standard does not
define modeling behavior of specific memories. The standard relies on table
based modeling constructs to transform the existing behavioral modeling
techniques to model memories into an equivalent structural/primitive based
modeling style. The scope of the memory model standard is currently
restricted to ASIC memories for static RAMs and ROMs.
Muti-source Interconnect Timing Simulation
------------------------------------------
The interconnect timing model as defined in VITAL-1995 is not accurate for
deep sub-micron ASIC libraries of today as it lumps a single interconnect
delay at the cell input. There is a need for being able to simulate
different delays across different interconnect paths leading up to an input
port.
VITAL-1999/2000 enables support of timing back annotation from multiple
INTERCONNECT statements in SDF (corresponding to multiple sources) leading
to a single input port. Furthermore simulation of interconnect delays in the
VITAL standard has been enhanced to handle different source to load delays
for each source of a input port which is stored is a virtual delay table.
The proposed change will mandate that the VITAL compliant VHDL simulator
maintain the backannotated delays from all the sources of an input port (a
load) and select delay for a change on the input port depending on the
source causing this change.
VITAL Level 1 Compliant Skew Checks
-----------------------------------
SKEW timing checks have become increasingly important in ASIC cell models
and in some cases it is detrimental to the functional behavior of the cell.
VITAL-1999/2000 enables specification of SKEW timing procedures in VITAL
Level 1 models. The implementation is a time based skew in which any two
signals are allowed to remain in a specified state for a maximum of tskew
time. If this constraint is violated then a skew violation is reported.
Improvements to VITAL setup and hold checks
-------------------------------------------
Several improvements have been incorporated to the behavior of setup, hold,
recovery and removal checks in VITAL-1999/2000. This includes accurate
boundary condition behavior, enhanced accuracy in timing violation reporting
in the presence of negative timing values, and enhanced condition handling
with more control over specifying Boolean conditions for test and reference
signal changes. Several bugs related to the InternalTimingCheck procedure
in VITAL timing package have been fixed. This may cause some changes to the
behavior of current VITAL models but will certainly eliminate any sign-off
issues found with VITAL-1995 versions of the libraries in the timing checks
area.
Invitation to Participate
-------------------------
If you design with VHDL and VITAL, are an ASIC/FPGA vendor or developer of
simulation technology which supports VITAL, you will want to attend this
workshop. Simply reply to this message to RSVP and a seat will be reserved
for you. HURRY, seats are limited and available on a first-come,
first-serve basis. And, to take advantage of this free workshop, you *must*
register by October 8th.
Sincerely,
Dennis Brophy
Chair, IEEE 1076.4 VITAL TAG
-- Dennis Brophy Email: dennisb@model.com Director of Strategic Business Development Phone: +1 (503) 526-1694 Model Technology Inc. Fax: +1 (503) 526-5473 10450 SW Nimbus Ave, Suite R Mobile: +1 (503) 706-8987 Portland, OR 97223-4347 Home Fax: +1 (503) 579-2664