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International HDL Conference 2000 CALL FOR PAPERS
March 8-10, 2000
San Jose Doubletree Hotel, San Jose, CA
www.hdlcon.org
CONFERENCE THEME:
HDLs, Beyond RTL--The Undiscovered Country
The HDL Conference is the forum for Innovative HDL Design techniques
targeting next generation and SOC designs. Now is your opportunity
to participate by submitting a paper on one of the topics listed
below, or on some unique topic of your own. Here is your chance to be
recognized by a prestigious group of designers and colleagues.
Papers, Tutorial proposals and Panel suggestions are due
DECEMBER 15, 1999
Papers should be between 1500 and 3000 words, double-spaced with
1-inch borders. It may contain as many diagrams as needed to
illustrate your key points, but please limit the paper to a MAXIMUM of
8 pages. (Longer papers may be rejected without further review.) One
page abstracts are acceptable under the condition that if accepted, a
full manuscript must be prepared for the Conference Proceedings.
Panel proposals should include an abstract of the topic, a panel
moderator and a list of proposed panelists.
Tutorial Abstracts should indicate the topic being proposed and a
brief biography with contact information for each presenter.
Suggested topics include:
SYSTEM-LEVEL DESIGN
S1. Hardware/Software Codesign
S2. Behavioral Coding and Synthesis
S3. VHDL/Verilog Cosimulation
S4. VHDL/Verilog and C Working Together
S5. Mixed-Signal Simulation
S6. Cycle-Based Coding Techniques
S7. Formal Verification
S8. Architectural Design Trade-offs
S9. System-on-Chip Design Techniques
S10. Advanced VHDL/Verilog Applications
S11. Emulation
S12. Design for Test
S13. Testbench Support
S14. Virtual Prototyping
S15. Reconfigurable Computing
S16. Performance Modeling
S17. Intellectual Property Capture, Protection, & Distribution
S18. Simulation Techniques
ASIC DESIGN
A1. Design Reuse
A2. Deep Sub-Micron Design Issues
A3. Constraint-Driven Synthesis
A4. ASIC Computer (SoC)
A5. Simulating Extremely Large ASICs
A6. Floorplanning Your RTL
A7. Advanced Techniques for Faster Simulation and Synthesis
FPGA DESIGN
F1. Mixed-Level Design (Schematic + RTL)
F2. Architecture Specific Optimization Techniques
F3. Multiple-FPGA Partitioning and Testing
F4. FPGA to ASIC Conversion
F5. Verification of Retargeted Devices
F6. Logic and State-Machine Design
F7. Timing Issues
All proposals should be emailed to papers@hdlcon.org in Word, PDF or
Postscript format only. Included must be complete contact information
for each author and a designated corresponding author and presenter.
For the latest information, see: www.hdlcon.org
For information concerning the conference contact:
Publications Department
c/o MP Associates, Inc.
5305 Spine Rd., Suite A
Boulder, CO 80301
tel: (303) 530-4562
fax: (303) 530-4334
email: info@hdlcon.org