VITAL-2000 Workshop in Europe


Subject: VITAL-2000 Workshop in Europe
From: Dennis Brophy (dennisb@model.com)
Date: Tue Jun 06 2000 - 23:51:25 PDT


Dear Colleague,

  If you plan to attend the VITAL-2000 workshop in Paris and have not yet
returned your RSVP, please RSVP to ecsi@wanadoo.fr with the information
requested at the end of this invitation.

-Dennis
_____________________________________________________________
VITAL-2000 Workshop

IBIS Hotel - Charles de Gaulle Aéroport/Gares
Paris, France
June 19, 2000
9:00-17:30

Organized by the European Electronic Chips
& Systems design Initiative (ECSI)

Co-sponsored by VHDL International

______________________________________________________________

Instructors
* Dennis Brophy, Model Technology - VITAL TAG Chair
* Jose DeCastro, Consultant - Lead VITAL Memory Model Developer

Overview
The workshop will highlight the new features of VITAL-2000
as contrasted to VITAL-1995. VITAL, the VHDL Initiative Towards
ASIC Libraries is currently in ballot by the IEEE. After the
Paris workshop, the VITAL Technical Action Group (TAG) will meet
to review the ballot comments. This workshop will serve as an
excellent venue for comments from European users, developers and
producers to meet and discuss the new additions to this standard.
There are several new features which have been added to the base
system along with some bug fixes. In addition, a new memory model
has been proposed. The workshop will detail this new memory model
and will highlight its use with several examples. There will be
several breaks during the day for you to meet with the workshop
instructors who also worked in the implementation of VITAL-2000.

______________________________________________________________

Agenda
08:00 - 09:00 Check-in/Registration
09:00 - 09:15 Workshop Introduction
                * Workshop Goals
                * VITAL Standardization Schedule
09:00 - 10:00 Basic Feature Updates
                * IEEE P1497 (SDF) Support
                * VHDL93 Support
                * SKEW Constraint Check
                * Multi-Source Interconnect timing simulation
                * Negative timing constraint modeling
                  for vector signals
10:00 - 10:30 BREAK
10:30 - 11:30 Basic Feature Updates (cont.)
                * Improvements to setup/hold (rec/rem) timing checks
                * Improvements to glitch handling and messaging
11:30 - 12:00 VITAL Memory Model
                * Function Specification
12:00 - 13:30 LUNCH
13:30 - 14:00 * Function Specification, cont.
14:00 - 14:30 * Corruption Specification
14:30 - 15:00 BREAK
15:30 - 16:30 * Memory Timing Specification
16:30 - 17:30 Workshop wrap-up - Q&A

Workshop fee is 100 euro
(including lunch and 2 coffee breaks)

______________________________________________________________

VITAL-2000 Workshop Reply Coupon
Name:
Company:
Address:
Country:
Phone: Fax:
E-mail:
Date:

Signature:

Please, fill-in and return to:

The European Electronic Chips & Systems design Initiative (ECSI)
Parc Equation
2, Avenue de Vignate
38610 Gières
France
Ph: +33 4 76 63 49 34
Fx: +33 4 76 42 87 87
E-mail: ecsi@wanadoo.fr
http://www.ecsi.org



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