Subject: HDLCon 2001 - VITAL-2000 Presentations
From: Dennis Brophy (dennisb@model.com)
Date: Fri Feb 23 2001 - 15:21:07 PST
Dear Colleague,
The 10th annual International HDL Conference & Exhibition (www.hdlcon.org)
is set to open next week at the Santa Clara, CA (USA) Marriott.
Session 1 on Thursday features two presentations on VITAL-2000. One
presentation is on advance ASIC sign-off features and the other is on the
new VITAL-2000 memory model. You can find more info about this session at
the following location: www.hdlcon.org/ses1.html. This session begins at
10:15am on Thursday March 1st. The cost for one day admission is $250 if
you are only interested in attending these sessions.
For those of you with plans to attend, we welcome you. For those of you who
cannot attend, we invite your input into the conference too! Just visit
Planet Analog (www.planetanalog.com) to register your voice on
analog/digital mixed-signal design.
The HDLCon-2001 program has been structured to inform and educate Systems
and Hardware designers about Verilog, VHDL, C/C++ and other languages for
RTL and System level designs. We do this with a combination of technical
sessions, panels, keynote address, keynote luncheon panel and exhibition.
The Thursday evening exhibition reception also has some fun in store - come
play "Who wants to be A Multi-Million Gate Designer."
As sponsor of the conference, Accellera organization looks forward to seeing
you there. A few details of the conference can be found below. Please feel
free to share this information with your colleagues.
Best regards,
Dennis Brophy
Chair, Accellera
---------- Int'l HDLCon 2001 Highlights ----------
PLANET ANALOG SURVEY
www.planetanalog.com
Steve Ohr, Editor at EE Times, is moderator of the Analog/Mixed-Signal panel
on Friday, March 2nd. As part of the panel, results from his pre-conference
survey will be discussed. What do you think mixed-signal design is? This
question is open to all designers, so visit the Planet Analog web site to
give him your feedback. This will take just a few seconds to complete.
Continue to watch the web site the following week for commentary on what the
panelist had to say and the results from others around the world.
KEYNOTE ADDRESS
www.hdlcon.org
Keynoter: Dr. Walden C. "Wally" Rhines, Mentor Graphics Corp.
Title: Discontinuities in Design -- Where's the Next Revolution?
For the last fifteen years, transition to HDL-based ASIC design, with a wide
variety of new analysis, verification and creation capabilities, has been
the primary driver of change in design methodology. The next major wave of
design methodology change will come from developing equivalent design
capabilities for FPGA-based system-on-chip platforms. Dr. Rhines will
address the capabilities that must be addressed, likely solutions and open
questions, as we move to the next major generation of HDL-based design.
KEYNOTE LUNCHEON PANEL
www.hdlcon.org/keynote.html
Moderator: John Cooley, ESNUG
Topic: Design Verification Languages: Are We Heading in the Right Direction?
Panelist:
- Bernd Braune, Get2Chip
- Simon Davidmann, Co-Design Automation
- Kevin Kranen, Synopsys, Inc.
- Stanley J. Krolikoski, Cadence Design Systems
- Maq Mannan, Chair IEEE 1364 Verilog
- John Sanquinetti, CynApps
- Dan Skilken, C Level Design
TUTORIALS
www.hdlcon.org/tutorials.html
- VHDL: A Practical Introduction
Paul Menchini, Menchini & Associates
- Verilog HDL: An Introduction to Modeling ASICs and FPGAs for Simulation
and Synthesis
Michael Ciletti, University of Colorado
- SystemC: An Introduction to Modeling Systems
Mike Baird, Willamette HDL, Inc.
- Vera: An Introduction to Using Vera for Design Verification
Chris Spear, Alex Fasan, Synopsys, Inc.
- VHDL Coding Styles for Hardware Design
Jim Lewis, Synth Works Design, Inc
- SuperLog: A Practical Approach to System Verification and Hardware Design
Peter Flake, Phil Moorby, Dave Rich, Co-Design Automation
- Rosetta: An Introduction to Using Rosetta for System Design
Perry Alexander, University of Kansas
EXHIBITION
www.hdlcon.org/exlist.html
More than 30 vendors will exhibit their products at HDLCon-2001. The
exhibition area is open at no charge. You simply must register for free
admission. The exhibition will be open March 1-2. On the first day of the
exhibition, there will be an evening reception with food and beverages -
also FREE. The evening reception will be from 5pm - 7pm, but does require
registration prior to 5pm.
TECHNICAL SESSIONS
www.hdlcon.org/techprog.html
There are six technical sessions held March 1-2 with presentations on more
than 35 technical papers accepted by the conference. Some of the topics
covered are:
- Working with the new VHDL & Verilog HDL Standards
- Design Techniques & Experiences Using HDLs
- SoC Design & Reconfigurable Computing
- Design Verification: Languages & Techniques
- Modeling & Verification Techniques Using C/C++
- Exploring Other Possibilities In HDL-Based Design
PANEL SESSIONS
www.hdlcon.org/friday.html
There are two panel sessions and will be held on March 2 with experts
debating issues from digital to analog and mixed-signal design and from
hardware to software. The panels are:
+ Mixed-Signal Design: Putting It All Together
Moderator: Steve Ohr, Editor - EE Times
http://www.hdlcon.org/pan1.html
Panelist:
- John Wright, American Micro Systems
- Ian Wilson, Antrim
- Doug Lundin, Avant!
- John Sanders, Cadence Design Systems, Inc.
- Rob Rutenbar, Carnegie Mellon University
- Gary L. Pratt, Mentor Graphics Corp.
- Rajit Chandra, Moscape, a Magma Company
- Kevin Cameron, National Semiconductor
+ Language Interoperability for Hardware-Software System Design
Moderator: Gabe Moretti, Editor - EDN
http://www.hdlcon.org/pan2.html
Panelist:
- Vassilios Gerousis, Infineon Technologies
- Anders Nordstrom, Nortel Networks
- Robert Clark, Panama Networks
- Steve Schulz, Texas Instruments
- Gary Spivey, Rincon Research
- Gregory D. Peterson, University of Tennessee
- Med Belhadj, Cisco Systems Co.
REGISTRATION FEES
http://www.hdlcon.org/reg.html
Exhibit Only Pass - FREE
Members Full Conference - $415
Non-Members Full Conference - $465
Students - $200
One-Day Only - $250
Tutorial Cost - $200
CONFERENCE LOCATION
www.marriotthotels.com/dpp/PropertyPage.asp?MarshaCode=SJCGA
The conference will be held at the Santa Clara Marriott located at 2700
Mission College Blvd, Santa Clara, CA 95054.
This archive was generated by hypermail 2b28 : Fri Feb 23 2001 - 15:27:02 PST