Subject: RE: Call for participation in VHDL std-logic WG
From: Dennis Brophy (dennisb@Model.com)
Date: Tue May 29 2001 - 09:23:23 PDT
Date: Sat, 26 May 2001 14:15:45 +0930
From: "Peter J. Ashenden" <peter@ashenden.com.au>
Organization: Ashenden Designs Pty Ltd
To: stds-vasg@majordomo.ieee.org, stds-dasc@dasc.org, vital@eda.org,
vital-tag@eda.org, sdf-sg@sphinx.cadence.com, vhdlsynth@vhdl.org
Subject: Call for participation in VHDL std-logic WG
Call for participation in Working Group for
IEEE P1164, Multi-Value Logic System
The IEEE Design Automation Standards Committee (DASC) invites you
to participate in the revision of IEEE Standard Multivalue Logic
System for VHDL Model Interoperability (Std_logic_1164). This
standard describes the VHDL data types used to model signals with
strong, weak, high-impedence and unknown values. It forms the
basis for other VHDL standards for RTL synthesis and ASIC library
models.
The standard was affirmed in 1993 and, according to IEEE rules,
is now due for reaffirmation or revision. A number of proposals
have been made for revision, and these have been prioritized for
immediate implementation or subsequent evaluation. Participation
is sought to develop these proposals into a draft standard. Work
items include developing and testing revisions to the standard
VHDL packages, developing revisions to the standard document, and
evaluating the draft standard in design scenarios. It is
expected that work on the proposals selected for immediate
implementation be completed and the draft be ready for ballot by
late 2001.
Participation is open to all interested parties. Voting
membership of the Working Group requires DASC membership.
Non-DASC members are invited to participate as observers.
Most of the work will be conducted via an email list. There will
be some in-person meetings held in conjunction with conferences,
in particular, DAC in USA in June and FDL in France in September.
Attendance at the in-person meetings is not a prerequisite.
If you would like to participate, please contact the Working
Group Chair, Peter Ashenden (mailto:peter@ashenden.com.au). You
can find more information at the Working Group's Web site at
www.eda.org/vhdl-std-logic/
-- Dr. Peter J. Ashenden peter@ashenden.com.au Ashenden Designs Pty. Ltd. www.ashenden.com.au PO Box 640 Ph/Fax: +61 8 8370 9106 Stirling, SA 5152 Mobile: +61 414 70 9106 Australia
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