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Q: What is the microSPARC-IIep design?
The microSPARC-IIep design is a highly integrated, low-cost implementation
of the SPARCTM-V8 architecture. The design includes on-chip
instruction and data caches, a low cost floating-point unit, a SPARC reference
Memory Management Unit (MMU) with a 32-entry TLB and interfaces to an EDO
DRAM (up to 256 Mbytes), and a 32-bit PCI bus. The microSPARC-IIep design
is developed using ASIC design methodology, which can be easily ported
to different processes from different vendors for speeds up to 125 MHz
in a 0.3 micron CMOS process.
Licensees can customize a version of the same design to achieve even
higher clock rates with smaller die size.
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Q: What applications is the microSPARC-IIep design
targeted for?
The microSPARC-IIep is targeted for "System-On-a-Chip" embedded
applications that require a high performance, low-cost SPARC core. The
efficient instruction set of the SPARC architecture along with the large
register file, which consists of eight windows with a total of 136 registers,
allows this single-issue design to offer better than 1 Dhrystone MIPS per
MHz--sufficient for many embedded applications, such as set-top boxes,
smart phones, and PDAs.
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Q: What instructions does the microSPARC-IIep design
support?
The microSPARC-IIep design implements the complete SPARC-V8 instruction
set. SPARC architecture V8 is the 32-bit version of the SPARC architecture,
which has been used in Sun Microsystems desktops and servers since 1987.
For details of the instruction set, see The SPARC Architecture Manual (version
8).
About the microSPARC-IIep Microarchitecture
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Q: What are the main functional units in the microSPARC-IIep
design?
The microSPARC-IIep design consists of the following major units:
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Integer Unit (IU)
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Floating Point Unit (FPU)
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Memory Management Unit (MMU)
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Instruction/Data Cache Unit (CC)
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Memory Interface Unit (MEMIF)
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PCI Controller Unit (PCIC)
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Q: Does the microSPARC-IIep design use any custom
blocks that licensees have to design? If so, what are they?
The microSPARC-IIep design uses a number of megacells that are to
be designed as custom blocks. Examples are:
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The register file, an eight-window, 136-entry register file with two read
ports and two write ports
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Instruction cache data and tag RAMs
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Data cache data and tag RAMs
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32-entry TLB
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The ROM for FPU microcode
These megacells are high-level behavioral models in the microSPARC-IIep
Verilog design.
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Q: What is the size and power dissipation for the
microSPARC-IIep design?
The microSPARC-IIep design uses a 16-Kbyte instruction cache and
an 8-Kbyte data cache. To save area and power, licensees can modify the
design and use smaller cache sizes. The size and power dissipation of the
microSPARC-IIep design depends on the size of the caches used as well as
the following two parameters:
The process geometry and the number of metal layers used The design
methodology (ASIC versus the custom design approach)
Licensees should synthesize the design with their own libraries and
compute the accurate gate count from the results. They can then estimate
the size and power based on the gate count, frequency, megacell design
data, and their process or design methodology.
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Q: What is the frequency at which the microSPARC-IIep
design can run?
The microSPARC-IIep design is a RTL design and can be targeted to
any process and library. The frequency at which it can run depends on the
process and the library in which it is designed. The Operating frequency
would to be from 0-150MHz in 0.25u technology and 0-200MHz in 0.18u technology.
Sun has demonstrated an implementation of the microSPARC-IIep design using
an ASIC methodology in a 0.3 micron CMOS process, which runs at speeds
of 100-120 MHz.
Designs with the microSPARC-IIep Design
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Q: What are the deliverables for the microSPARC-IIep
design?
The microSPARC-IIep design database includes the following:
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The Verilog RTL source for the design
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The SPARC instruction simulator
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The simulation environment for the design
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The source for the test suites that are used to verify the design Documentation
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The SPARC Architecture Manual/Version 8
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microSPARC-IIep User's Manual
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microSPARC-IIep Validation Catalog
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microSPARC-IIep Megacell Reference
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Multiprocessor SPARC Architecture Simulator (MPSAS) User's Guide
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Multiprocessor SPARC Architecture Simulator (MPSAS) Programmer's Guide
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Q: What is the format in which the microSPARC-IIep
design is available?
The microSPARC-IIep design, developed in Verilog's RTL language,
consists of high-level behavioral megacell models and fully synthesizable
logic for the rest of the design. You can synthesize the design with a
cell library of your preference. Synthesis results and the clock frequency
that you achieve depend on your synthesis approach and cell library.
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Q: Is the microSPARC-IIep design developed for
a particular process?
No. The Verilog model of the microSPARC-IIep design contains no
process-specific data, hence the design can be retargeted to any process.
We recommend, however, that you choose a 0.3 micron or better process to
achieve the expected clock frequency with minimum customization.
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Q: What CAD design tools are used in the microSPARC-IIep
design?
Two major CAD tools are used in the design:
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Verilog (for RTL description): The RTL is simulated or verified with Cadence
Verilog-XL or Synopsys VCS.
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Synthesis: The RTL is synthesized with Synopsys Design Compiler.
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Q: What platforms is the microSPARC-IIep design
environment based on?
Sparc and SolarisTM platforms are the basis for the microSPARC-IIep.
Both platforms are fully supported. However, porting the simulation environment
and tools to other platforms may be possible, although these are not tested
or verified.
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Q: Can licensees define their own instructions?
One key factor in the compliance with the SPARC architecture is
its Instruction Set Architecture (ISA). For tools and applications to function
properly on all implementations based on the microSPARC-IIep design, the
ISA must be the same across all designs. The SPARC V8 architecture reserves
a number of opcodes as "user-defined" instructions, such as coprocessor
instructions. However, licensees must be aware that such instructions are
not supported by standard tools. Of course, licensees need comply with
the ISA only if they intend to use the final design in commercial products
that carry the SPARC V8 logo.
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Q: Can licensees make microarchitectural enhancements
to the microSPARC-IIep design?
The microSPARC-IIep design is an implementation of the SPARC V8
ISA. Licensees can use this design as a reference to optimize, enhance,
and reduce the costs of their implementations or modify it for use in applications.
The final designs must, however, pass the compliance test suite if they
are intended for use in commercial products that carry the SPARC V8 logo.
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Q: What is the microSPARC-IIep design Validation
Test Suite? What does it test?
The microSPARC-IIep Validation Test Suite, a suite of tests written
in SPARC assembly language, verifies the functionality of the design. This
test suite consists of many tests that are targeted at testing different
units within the design and verifying the entire instruction set and corner
cases for different instruction sequences.
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Q: How do licensees access the microSPARC-IIep
design VTS?
Licensees can access the microSPARC-IIep VTS as part of the design
database available on the Sun Community Source License (CSL) Web site.
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Q: Are chips that are based on the microSPARC-IIep
design available today?
The microSPARC-IIep design database is the exact design database
that is used in fabricating the microSPARC-IIep chip, a product from Sun
Microsystems, Inc. The functionality of this chip has been fully verified
in a number of designs from Sun as well as customers who have used it.
The microSPARC-IIep chip has been in production since 1998.
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Q: Has Sun designed any reference boards based
on the microSPARC-IIep design?
Sun has designed several board products based on the microSPARC-IIep
chip, one of which is called CP1200, a compact PCI board for use in embedded
applications. Another product is the JavaEngineTM 1 board, which
is mainly used as a demonstration for the JavaOSTM operating
system running on the microSPARC-IIep chip.
Software and Development Tools for the microSPARC-IIe Design
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Q: Is there a Java virtual machine port for the
microSPARC-IIep design?
Sun has ported an early version of the JavaOS operating system (JDK
1.1.3) to the JavaEngine 1 board based on the microSPARC-IIep design. Sun
may make this port available to licensees in the future.
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Q: What other operating systems are supported?
In addition to the JavaOS operating systems, VxWorks has also been
ported to the CP1200 CompactPCI (cPCI) board, which is based on the microSPARC-IIep
design. Linux is also supported on the microSPARC-IIep processor.
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Q: What development tools are available for the
microSPARC-IIep design?
The microSPARC-IIep design being a SPARC-compliant design, you can
use all standard SPARC development tools for development projects.
