Xilinx
has just unveiled a new 48-lead Chip Scale Package (CSP) that offers all
the benefits of an extremely small form factor in a rugged ball grid array
package. This package is ideally suited for a growing number of space
premium applications where minimum board space and package thickness are
important. Applications include PCMCIA cards, PC add-in cards, and
portable and wireless designs.
We
are the first non-memory manufacturer, and programmable logic supplier,
to have CSP technology available now. The first Xilinx CSP, the XC9536
ISP CPLD, has 48 pins arranged in a 7 x 7 ball array configuration
using a 0.8 millimeter ball pitch.
The
footprint (area) of the Xilinx 48 pin CSP is about one third (34%) of VQ44
and one sixth (16%) of PC44. With chip scale packages, the requirements
for handling and lead coplanarity are greatly reduced because there are
no fragile leads to bend.
The
die is attached to the substrate and wire bonded using industry-standard
techniques. System manufacturers using CSPs can benefit from CPLD
speed and cost improvements (die shrinks). It is also important to
note that there will be no change in package size and ball pitch with die
shrinks. Thermal resistance of the package (theta JA) is 45.5 degrees
C per watt, which is comparable to the VQ44 package at about 42 degrees
C per watt.
The
package is also thin (1.3 to 1.8mm) and light weight (0.17 gram) which
makes it ideally suited for weight conscious portable applications like
cellular phones, hand held inventory, bar code reader systems and personal
digital assistants.
XC9536
Industry's First CPLD in CSP
The XC9536
is the first XC9500 FastFLASH ISP family device offered in this package.
It features 34 I/Os, and full IEEE 1149.1 JTAG support, 10,000 program/erase
cycles and 20 years of data retention. The XC9536 also features unmatched
logic flexibility and the industry's best CPLD pin-locking. |
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