Xilinx Application Briefs are technical papers describing the advantages of Xilinx products, especially versus competing solutions.

Summaries

The Xilinx XC4000 Series Select-RAM offers the best size flexibility and at the same time offers high-speed operation with very little waste.

The Xilinx XC4000E/EX/XL families offer low-power architectures which have been optimized for high-speed, high-density operation, giving the customer reliable operation with many package options while satisfying the need for very high performance designs. Xilinx devices consume one-half to one-third the power of competitive devices.

Detailed analysis shows that Select-RAM is the most silicon-efficient implementation for FPGA memory. Due to the Dual-Port RAM capability it also offers maximum bandwidth for most applications.

The ability to maintain fixed I/O pin locations during PLD design and to migrate designs between footprint-compatible PLDs of varying densities helps isolate printed circuit board design from logic changes within the PLD device, thereby accelerating time-to-market and accommodating design changes throughout a product's life.

The new XC4000X family (XC4000EX/XL/XV) includes large amounts of new routing resources, necessary to support today's larger designs. These resources are detailed and compared with the XC4000E, and with ORCA devices from Lucent Technologies (formerly AT&T).

This paper examines some general concepts concerning Phase Locked Loop (PLL) usage and their application in programmable logic devices. A critique of a newly-announced PLL implementation for FPGAs also is included.

Reusable logic cores provide an efficient means of embedding common logic functions in high-density FPGA designs. The rich feature set of the XC4000-Series FPGA devices makes them the ideal choice for core-based system design.

This application brief presents benchmarks that demonstrate the superior pin-locking capability of the Xilinx XC9500 CPLDs. These benchmarks are based on typical applications and demonstrate the benefits of a highly routable switch matrix and wide function block fan-in when iterating pinlocked designs. The Xilinx results are compared to other vendors' CPLDs using their latest production fitters, proving that the Xilinx XC9500 family is the industry's best pin-locking CPLD.

The Xilinx FastFLASH technology, used in the XC9500 family, provides key advantages in reliability, density, and performance. This overview describes the FastFLASH process technology and compares it with EEPROM technology.

As an alternative to "gate counting", the capacity of lookup-table-based FPGAs can be measured more directly and objectively by examining the number of available "logic cells".

A simple method is presented for estimating power dissipation in XC4000X FPGAs. This method is targeted for early estimates during design conceptualization before detailed design information is available.

Performance data (in terms of circuit speed) is provided for several key logic and routing functions implemented in XC4000XL-09 FPGAs, for purposes of overall system performance estimation. Performance data also is provided for equivalent implementations in the Altera FLEX 10K-2 family devices.

Retargeting XC7200/XC7300 designs to the XC9500 CPLD family can be as simple as changing the device type in the Design Manager and refitting the design. The uniform architecture of the XC9500 simplifies design translation. This document assumes a version 4.2 or later Xilinx design file for the original XC7200/XC7300 format. Xilinx M1 design software translation to the XC9500 is also assumed.