Schematic Entry

Application Notes

Title	Size
XC5200 Macro Library Supplement	150 KB
Migrating Cadence Designs to M1	50 KB
XAPP043: Improving XC4000 Design Performance	160 KB
XAPP057: Using Select-RAM Memory in XC4000 Series FPGAs	210 KB
XAPP062: Design Migration from XC4000 to XC4000E	60 KB

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XCell Articles

Title	Issue
Q&A: Foundation Series Software	Q2 '98
Q&A: Viewlogic	Q2 '98
Xilinx System-Level Design Capabilities with Active-CAD from Aldec	Q1 '98
Xilinx Now Shipping Cadence Interface Kit	Q2 '97
ProSeries Users Upgraded with Workview Office	Q1 '97
OrCAD to Provide Support for OrCAD-Xilinx Interface	Q1 '97
Retargeting Designs in Mentor Design Architect	Q1 '96

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