Timing Analysis

Title	Size
XAPP095: Set-up and Hold Times	10 KB
XAPP071: Using the XC9500 Timing Model	60 KB
XAPP094: Metastable Recovery (FPGAs)	20 KB
XAPP077: Metastability Considerations (CPLDs)	30 KB
XAPP096: Overshoot and Undershoot	10 KB
XAPP011: LCA Speed Estimation: Asking the Right Question	10 KB
XAPP018: Estimating the Performance of XC4000E Adders and Counters	40 KB
XAPP045: XC4000 Series Technical Information (Capacitive Loading, Ground Bounce)	30 KB
XAPP024: XC3000 Series Technical Information (I/O Characteristics, Oscillator)	110 KB

Title	Size
XBRF015: Speed Metrics for High-Performance FPGAs	100 KB
XBRF006: PLL Design Techniques and Usage in FPGA Design	40 KB

Title	Issue
Printed Circuit Board Design Considerations	Q2 '98
XC4000XL FPGAs Interface to SDRAMs at 100MHz	Q2 '98
Self-Initiated Global Reset	Q2 '98
CMOS I/O Characteristics	Q2 '98
Low-Power FPGA Achieves 400 MHz Performance	Q2 '98
Using IBIS Specifications	Q1 '98
A 200-MHz Pulse Generator	Q1 '98
An Innovative Way to Reduce Electromagnetic Interference	Q1 '98
High-Performance Design: XC4000XL-1 FPGAs Exceed 100MHz	Q3 '97
HardWire: Ensuring a Successful FPGA to ASIC Conversion	Q3 '97
Trouble-Free Switching Between Clocks	Q1 '97
A Look at "Minimum" Delays	Q2 '96
Power, Package, and Performance: Trading Off Among the Three P's	Q3 '96
Metastability Recovery in Xilinx FPGAs	Q3 '96
Using Decoupling Capacitors	Q1 '96
Synchronous RAM Timing in the XC4000E FPGA	Q4 '95
User-Defined Schmitt Triggers	Q4 '95
Low-Pass Filtering of Noisy Inputs	Q3 '95