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In this Q4 '95 issue... 

• General News

Customer Success Story: FPGAs Control ATM Connections to French Telecom Network 
Xilinx Earns ISO 9002 Certification 
 
• Hints and Issues

Synchronous RAM Improves System Speed 
On-chip, distributed memory facilitates the efficient implementation of register banks, status registers and high-speed FIFO buffers that bridge the gap between subsystems that have different access times and data burst rates 
Synchronous RAM Timing in the XC4000E FPGA 
With proper attention to address routing delays, synchronous RAMs can be operated at, or close to, the maximum clock frequency, as determined by the minimum write cycle time 
See also: Memory Applications 
User-Defined Schmitt Triggers