Answers Database
ViewSynthesis: Flow for black box instantiation
Record #2689
Product Family: Software
Product Line: ViewLogic
Problem Title:
ViewSynthesis: Flow for black box instantiation
Problem Description:
Keywords: LogiBLOX, ViewSynthesis, symbol, EDIFNETO, instantiate, black box
EDN, NGO, XNF, Aurora
Urgency: Standard
When a component that is not found in any project library -- that is, no
matching symbol is found via the viewdraw.ini search path -- is instantiated
in the VHDL code ViewSynthesis writes it out as a black box. However,
ViewSynthesis denotes the symbol as composite type in the resulting WIR file.
This will cause EDIFNETO to fail when you attempt to write out a Xilinx-level
netlist, since the composite symbol has no corresponding WIR file. This
causes a problem for instantiated LogiBLOX components, since no pre-existing
symbols will be found.
Note: The procedure documented in this solution will not work for Aurora
Synthesis in Workview Office 7.4. See (Xilinx Solution 3233) for details on
the proper procedure.
Solution 1:
This procedure will work for any instantiated black boxes: XNF, EDIF, or NGO
files from any source.
1- Load the VHDL design file(s) in Viewsynthesis.
2- Under the Global Synthesis settings, under the Operation tab, Select
"Generate Schematic".
3- Compile and synthesize the code.
4- Open the symbols representing black boxes in ViewDraw and add two symbol
properties to each. Open the "Symbol Properties" window by double clicking
the left mouse button and add "LEVEL=XILINX" and "FILE=design.type", where
"design" is the name of the instantiated module and "type" is XNF, EDN or NGO.
Save the Symbol.
5- Open the top level schematic in ViewDraw. Save and check the Schematic.
6- M1 users: Create an EDIF file using the EDIF GUI. To add this command to
the ViewDraw Tools menu, see (Xilinx Solution 1985).
7- Open the Xilinx Design Manager and select the top level WIR file (XACTstep
6.0 users) or the .EDN file (M1 users). Place and route the design.
End of Record #2689
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