Answers Database

Viewlogic: Aurora Synthesis 7.4 produces global GND and VDD instances inschematics; NGDBUILD fails


Record #3233

Product Family:  Software

Product Line:  ViewLogic

Problem Title:
Viewlogic: Aurora Synthesis 7.4 produces global GND and VDD instances
inschematics; NGDBUILD fails



Problem Description:
Keywords: Aurora, ViewSynthesis, VHDL, Viewlogic, ViewGen, GND, VDD, basnu, 7.4
	  NGDBUILD, EDIF2NGD, multiple drivers, global net

Urgency: Hot

General Description:
Using Aurora Synthesis version 7.4, if schematics are generated (via the
Generate Schematic checkbox in Global Synthesis Settings), then NGDBUILD will
fail with the following error:

WARNING:basnu - global net "GND" has no load
ERROR:basnu - global net "GND" has multiple drivers

The wire files created by Aurora have G GND and G VDD instances, which produce
these GND and VDD instances when ViewGen is run.  These instances appear on
every schematic, but they are never used.


Solution 1:

Do not generate schematics when using Aurora Synthesis and M1.

If schematics are desired (for simulation annotation, for example), do not
generate them until after the EDIF file has be written and passed to M1.  If
re-synthesis is required, delete all the .1 files in the SCH directory before
re-synthesizing and re-creating the EDIF file.

When creating schematics for simulation annotation, do not check the "Generate
Schematic" box; use ViewGen to generate the schematics for the design.



Solution 2:

If black boxes are instantiated in the VHDL design (representing XNF, EDIF or
NGO files) as described in (Xilinx Solution 2689), attributes must be placed
on symbols before the design will be able to be merged properly by the Xilinx
tools.

1- Load the toplevel.vhd file in Viewsynthesis.

2- Compile and synthesize the code.  Do not generate schematics.

3- Even though schematics have not been created, symbols have.	Open the
symbols representing black boxes in ViewDraw and add two symbol properties to
each.  Open the "Symbol Properties" window by double clicking the left mouse
button and add "LEVEL=XILINX" and "FILE=design.type", where "design" is the
name of the instantiated module and "type" is XNF, EDN or NGO.	Save the
Symbol.

4- Return to Aurora Synthesis and rerun the final step: "Logic Optimization
and Mapping Current Design".  This step is required to update the WIR files
with the new symbol information.

5- M1 users: Create an EDIF file using the EDIF GUI.  To add this command to
the ViewDraw Tools menu, see (Xilinx Solution 1985).

6- Open the Xilinx Design Manager and select the top level WIR file (XACTstep
6.0 users) or the .EDN file (M1 users). Place and route the design.



End of Record #3233