Answers Database
VERILOG-XL: SDF Annotator gives "SDFA Error: Could not find path IN to OUT"
Record #2750
Product Family: Software
Product Line: Cadence
Problem Title:
VERILOG-XL: SDF Annotator gives "SDFA Error: Could not find path IN to
OUT"
Problem Description:
Keywords: verilog simulation, timing simulation, SDF
Urgency: Standard
Upon doing a timing simulation in Verilog-XL, you may receive
the following errors if you also use the +delay_mode_unit
option:
time_sim.sdf L18: SDFA Error: Could not find path IN to OUT in instan
ce test.uut.p1$i27
time_sim.sdf L183: SDFA Error: Could not find path CTL to OUT in inst
ance test.uut.\p1$i29.GTS.TRI_737
time_sim.sdf L233: SDFA Error: Could not find path IN0 to OUT in inst
ance test.uut.\p1$i40/p1$i23/p1$i3
time_sim.sdf L281: SDFA Error: Could not find path ADR0 to OUT in ins
tance test.uut.\p1$i40/p1$i20/i18
time_sim.sdf L295: SDFA Error: Failed to find WIDTH timingcheck
time_sim.sdf L297: SDFA Error: Failed to find SETUP timingcheck
You may not use the +delay_mode_unit option while also doing a
SDF annotation. The SDF file is the Standard Delay Format,
file, and it contains all the timing information for the
design).
Solution 1:
If your goal is to do a simulation with unit delays on a
Verilog file generated to do timing simulation, edit the Verilog file (.v) and c
omment out the line that calls the
"$sdf_annotate" function with a double slash (//).
Example:
In the file "time_sim.v", generated by ngd2ver by the M1
tools when doing a Verilog timing simulation, you will find:
.....
initial $sdf_annotate("time_sim.sdf");
Change this to:
// initial $sdf_annotate("time_sim.sdf");
Remember to comment out the "initial" statement
associated with this function call when you comment the
sdf_annotate function call.
If you wish to toggle between full timing and unit delay
simulation without having to modify your Verilog netlist each
time, see (Xilinx Solution #2650) for instructions on
specifying the SDF file from the command line.
End of Record #2750
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