Answers Database

9500: What are the differences between reset lines in simulation and onthe device


Record #3518

Product Family:  Hardware

Product Line:  9500

Problem Title:
9500:  What are the differences between reset lines in simulation and
onthe device



Problem Description:
Keywords:  PRLD, GSR, GTS, 9500, CPLD, simulation

Urgency:  Standard

General Description:  What is the difference between the
simulation signals PRLD/MRESET and the signals used by the
global buffers GTS and GSR?


Solution 1:

PRLD is simply a simulation signal only.  During
configuration and power-up all flip flops in the device
are set to a known level, regardless of what the user does.

However, most timing simulators are unable to simulate this
behavior, thus PRLD must be used to initialize all
flip flops in the simulation.

For more details about PLRD see (Xilinx Solution 2471).



Solution 2:

The GTS and GSR are global buffers that route to either
all Tri-state enables or all Set/Reset pins on flip flops
respectively.

To simulate these signals in a simulation, stimulus must be
put on the net names.

The GTS and GSR buffers must be routed on schematic or
inferred in your HDL code to be used, unlike the GSR signal
found in Xilinx FPGAs.



End of Record #3518