FPGA Express Interface - Tips and Techniques

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	Solution 3781 - XNF Bus Style option explained
	Solution 3583 - How to avoid latch inferences in FPGA Express
	Solution 3301 - How to create HDL macros for Foundation F1.4 schematics
	Solution 2734 - HDL Simulation of HDL only designs synthesized with FPGA Express
	Solution 2230 - Using RLOC Origins with Express-generated RPMs