Cadence Interface - Xilinx M1 Library Status

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Concept:

Families supported:

• XC3000A and XC3100A
• XC4000E/EX/XL/XV
• XC5200
• XC9500

The Libraries for these architectures are available on the Xilinx Alliance 1.4 CD. Spartan and SpartanXL libraries will be added in the Xilinx Alliance 1.5 release. For users wishing to target the Spartan device with the Alliance 1.4 release, The XC4000E library may be used. See Xilinx Solution 3441 for details.

CONCEPT2XIL Netlister: You may obtain the CONCEPT2XIL netlister from Cadence's ftp site. See Solution 2766 for details.

XIL2CDS: Projected availability for XIL2CDS, the tool developed by Cadence for board level integration into Concept, is approximately January 1998. See Solution 2943 for details.

Composer:

• Alliance support for Spartan, XC4000E/EX/XL/XV and XC9500 currently not scheduled.
• Use Cadence release 9604 with XACT 5.2.1 if you wish to target 2K, 3K, 4K and 7K architectures.

Synergy:

Cadence

Verilog-XL:

Families supported:

• XC3000A and XC3100A
• XC4000E/EX/XL/XV
• XC5200
• XC9500

The Verilog Unified Libraries supporting Concept functional simulation for these architectures are available on the Xilinx Alliance 1.4 CD. Spartan and SpartanXL support will be added in the Xilinx Alliance 1.5 release.

Library and Interface Ownership

Who will develop and maintain the Xilinx libraries?

As of March 1, 1997, Xilinx took over full support of the Concept, Composer, and Verilog-XL libraries, and is the sole supplier of these libraries. Note, however, that only Concept and Verilog-XL are supported in the Xilinx Alliance 1.4 release. There is no planned future support for Composer.

Contact Distribution

Are the libraries free or purchased, and who distributes them?

With the Alliance 1.4 release, the following are supplied as part of the Xilinx Alliance Standard Package, at no additional charge:

• Concept libraries
• Verilog-XL Unified Libraries for Concept functional simulation (verilogxce4000ex, etc.)

The following is supplied as part of the Alliance Core Tools to support post-NGDBuild functional simulation, post-MAP timing simulation, and post-route timing simulation:

• Verilog SIMPRIM Libraries for post-NGDBUILD, post-MAP and post-route simulation

The following will continue to be shipped by Cadence until and including the 97A release:

• Pre-M1, XACT 5.x-compatible Concept, Composer and Verilog libraries

Verilog-Only Users

What if I only need a Verilog interface and library package?

In the Alliance 1.4 release, you will only need:

• Verilog UNISIM Libraries for RTL and Post-Synthesis simulation
• NGD2VER for Post-M1 Verilog simulation netlisting
• Verilog SIMPRIM Libraries for Post-NGDBUILD, Post-MAP, and Post-PAR simultions

These are included as part of the Xilinx Alliance 1.4 Core Tools, at no additional charge.

Updates

How are libraries updated between releases and in conjunction with them?

The following will be updated in each Xilinx release:

• Concept libraries
• Verilog-XL Unified libraries
• Verilog UNISIM libraries
• Verilog SIMPRIM libraries

Patches may be provided for these libraries as the need arises via Xilinx ftp, located at: ftp://ftp.xilinx.com/pub/swhelp/cadence.

Ongoing updates to the following product(s) will be available on the Cadence release CDs:

• Synergy libraries

Archives and updates for the Synergy libraries and the following Cadence Concept netlisters will be available on the Cadence ftp site, ftp://ftp.cadence.com/patches:

• Concept2xil
• XIL2CDS