After placement and mapping the Xilinx tools generate VHDL or Verilog netlist with SDF file for back annotating timing delays. Test Bench template is automatically generated with the -tb option available in the Xilinx tools. The designer fills the template with vectors and verifies the design with MTI tools. VITAL compliant libraries for all architectures are available with the Xilinx tools. 

Model Technology has three main products 

Model Technology Products Summary Info.....for more details check their web site at:  http://www.model.com 
 

Major Features: 

• Model Technology offers the best value, Model Technology develops and markets HDL simulation solutions for VHDL, Verilog and mixed-HDL designs for both workstations and PCs
• V-System products are intuitive easy to learn and use
• For teams simulating million -gate ASICs to those designing FPGAs or PLDs
• Full-features VHDL simulator supporting IEEE-1076-87, BITAL 2.2b and VITAL '95
• Direct Compile architecture results in the industry's fastest compile times and simulation performance, design and library portability with machine-independent object code
• Tcl/Tk technology provides an easy-to-use, customizable user interface with dynamically linked windows for fast and simple debugging
• V-System/VHDL is truly the world's most widely used VHDL simulator and is available on workstation and PC platforms. 
• V-System/VLOG is the Verilog version
• V-System/PLUS allows for a seamless mixing of VHDL and Verilog with V-System/PLUS Single kernel Simulation (SKS) enables direct instantiation of Verilog modules, VHDL entities or VHDL configurations, without unwanted wrappers. MIxing of HDL design entities can occur at multiple levels of the design hierarchy.