OrCAD Express / Xilinx Alliance Series Design Flow and Interface
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The design flow starts with the Express schematic editor using the Xilinx
Unified Library components and (optionally) LogiBLOX components. Use VHDL
RTL source to any degree.
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After design entry, simulate schematics and/or VHDL RTL source in Express
Simulate.
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Synthesize and optimize performance with Express Compile to generate an
EDIF netlist for the Alliance Series place and route tools or functional
simulation.
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Launch Alliance Series with Express Build to translate EDIF files created
by Express Compile into an .ngo file, then merge all .ngo files created
by LogiBLOX, Unified Library Macros, and netlists into an .ngd file.
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After place-and-route by M1, a timing-based VITAL/VHDL model (.vhd) netlist
file and standard delay format (.sdf) file is read by Express Simulate
for timing simulation.
OrCAD Express is the ideal design entry tool to express the designer’s
intent. The schematic editor makes it easy to describe the design hierarchy
with block diagrams. Powerful design management, online design rule checking,
and standard interfaces including: VHDL and EDIF 2 0 0. The built-in programmer’s
editor is ideal for composing VHDL and an automatic syntax check confirms
source code before it reaches the simulator. Design rule checks detect
data flow problems across schematic and VHDL design modules. Integrated
LogiBLOX allows interactive specification and symbols to be created automatically.
Below is the OrCAD Express/Alliance Series Design Flow:
Below is the OrCAD Express/Alliance Series Software Design Flow illustrating
design entry, functional and timing simulation.
You can download the attached Word documents for more information:
OrCAD Express Overview and Orcad
Express/Xilinx Alliance Series Overview.
For further information, click on the Technical Support hyperlink in
the navigation bar at the bottom of this page.
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Overview