The following example calculations and table are based on a ns board trace delay. Please enter your anticipated board trace delay to customize the results.
The table on the left shows the highest frequencies available for a given combination of Virtex and ZBT SRAM speed grades. The Virtex 'clock to out' and 'setup' timing numbers for various speed grades are shown in the top rows. The ZBT SRAM 'clock to out' and 'setup' timing numbers are displayed in the first few columns on the left. The speed grades for the ZBT SRAM devices correspond to the clock period. The table on the right shows the margin or 'slack', for both read and write operations. For example, a -7 part can operate at a 7 ns clock period or at a maximum frequency of 142.9 MHz. By submitting 0.3 ns for board trace delay in the calculator dialog below, the resultant table on the left suggests a -4 grade Virtex device matched with a -7 grade ZBT SRAM at 142.9 MHz.
To calculate the margin for read and write operations, we start with the initial board trace delay of ns. Using a -7 grade ZBT SRAM and a -5 grade Virtex FPGA, the margin for the read operation would be 0.8 ns and the margin for the write operation would be 1.1 ns. In this example, 0.8 ns can be added to board trace delay while achieving the maximum clock speed of 142.9 MHz. Alternately, by choosing board trace delay of 0, the timing margin for various combinations of speed grades can be calculated. The timing margin is the maximum board trace delay operating at the rated frequency. For an anticipated board trace delay of 0, the timing margin for using a -4 grade Virtex with a -6 grade ZBT SRAM is 0.3 ns for read and for write. With a board trace delay not greater than 0.3 ns, the interface will run at 166.7 MHz.
Note:
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