SAN JOSE, Calif., January 15, 2001—Xilinx, Inc. (NASDAQ:XLNX), the leader in programmable logic solutions, today announced the immediate availability of its next generation Virtex® series representing the first embodiment of the Xilinx® Platform FPGAs. For the first time in the industry, designers managing around signal integrity, system timing, electro-magnetic interference (EMI) issues, and design security have a programmable platform to address these challenges. Further, with the Virtex-II introduction, users can leverage the Xilinx IP-Immersion^TM technology to more easily integrate both soft and hard intellectual property (IP) cores. The Virtex-II devices announced today contain high-bandwidth performance, support for today's leading-edge I/O standards, and unprecedented memory capabilities that provide a viable alternative to ASICs. See also the Virtex-II question and answer document. A technical backgrounder is also available.

"The exponential rate of change of system performance is bringing new challenges for designers who are simultaneously facing shrinking time to market requirements. The Virtex-II family is a major leap forward in solving these challenges," said Dennis Segers, senior vice president and general manager of the Xilinx Advanced Products Group. "For example, with ever-increasing bandwidth requirements, system engineers face extreme signal integrity issues. Our XCITE^TM signal integrity technology in the Virtex-II FPGAs dramatically simplifies board design and maximizes system performance."

Platform for Signal Integrity 

The Virtex-II family addresses critical issues, such as complex board layout and signal distortion, using the industry's first digitally controlled impedance (DCI) technology. DCI eliminates drive strength differences due to process variations and maintains constant impedance even with temperature and voltage fluctuations. The Xilinx Controlled Impedance Technology (XCITE) capability uses two external reference resistors to hold input and output impedance for hundreds of I/O pins. Benefits include a reduction in on-board resistors with significantly lower system costs and fewer board re-spins. Eliminating hundreds of resistors using the XCITE technology, designers can reduce board layout complexity and increase reliability.

Platform for System Clocking

Each Virtex-II device has 16 pre-engineered low-skew clock networks to eliminate complex clock tree analysis, which is imperative in high performance designs. The Virtex-II devices also contain up to 12 digital clock managers (DCMs) for generating any frequency within the operating range and allowing clock edge placement accuracy down to one percent. On-chip and off-chip clock synchronization support with precise 50/50 duty cycle generation is ideal for double data rate (DDR) applications, such as RapidIO^TM, LDT^TM, and SPI-4.

"The new Virtex-II devices incorporate innovative circuit technologies that help address complex challenges in signal integrity, advanced clocking, and high-speed bus interfacing," said David Ayers, vice president of switching platforms and technologies for Lucent Technologies.

Platform for EMIControl Management

The Virtex-II family is the first programmable solution to provide innovative spread spectrum clocking technology to reduce EMI noise emissions. Digital spread spectrum (DSS) technology spreads the output clock frequency spectrum to reduce EMI and meet FCC regulations. This feature allows the designer to greatly reduce system cost and design cycles by minimizing board re-spins and eliminating expensive shielding.

System Security Solution

Design security is now available with the Virtex-II family through bitstream encryption. The bitstream is encrypted using a secure triple data encryption standard (DES) algorithm. The key is supplied through the IEEE 1149.1 (JTAG) interface, which is stored inside the chip using either a battery or other constant power supply. The encrypted bitstream is loaded into the FPGA with a specific key bank designated for decryption. This feature provides high design security to prevent design theft, and enables an entirely new business model for IP providers.

Key innovations in Virtex-II family

IP Immersion and Active Interconnect^TM technologies are two key revolutionary steps for embedding IP. The IP Immersion technology allows hard IP cores to be diffused at any coordinate within the Virtex fabric while maintaining smooth integration with the surrounding array. The Active Interconnect technology offers actively driven routing channels that ensure hard and soft IP cores maintain predictable, very high performance rates independent of their location within the array. Furthermore, Virtex-II family provides the fabric for embedded processors, gigabit serial performance, and analog signal support.

Platform FPGAs, the requirement of the future

The Virtex-II devices are the first offering in the new Xilinx Platform FPGA and represent a flexible solution that integrates a wide variety of hard and soft IP cores on a single device whose hardware and firmware can be upgraded at any time. The programmability of  the architecture reduces system development time yet enables a single Platform FPGA to be targeted at multiple applications.

Software and IP support available now

The Virtex-II devices are fully supported by the Xilinx software solutions, available since May. The latest release, version 3.2i of both the Alliance Series^TM and Foundation Series^TM Integrated Synthesis Environment (ISE^TM) software, improves the Xilinx design flow by accelerating place and route runtimes and supporting incremental and team design methodologies. In addition, advanced design flows including Modular and Incremental Design are all now available for use in designing Virtex-II FPGAs. Many cores are also available for the Virtex-II family. For more information, please go to www.xilinx.com/ipcenter.com.

The Virtex legacy

The new Virtex-II family offered today has many more industry-leading features that digital designers can employ today for high-end design: system bandwidth and a wide variety of I/O standards; high-bandwidth memory hierarchy; processing bandwidth with 0.6 Tera MAC DSP performance levels; and system timing bandwidth with DLLs running at over 400 MHz. For more complete information on the full feature set of Virtex-II device, visit the Virtex pages at the Xilinx web site.

Pricing, availability and packaging options

The newest member of the Virtex series ranges in density from 40,000 to 10 million system gates. Several packaging options are available for the family, including 1517-pin fine-pitch, 144-pin chip scale, and 957-pin flip chip ball grid array packages. The first members of the Virtex-II family, the XC2V40^TM (40,000 system gates), XC2V1000^TM (one million system gates), and XC2V6000^TM (six million system gates) devices are sampling now with the rest the family sampling by mid 2001. Pricing for the XC2V40, XC2V1000, and XC2V6000 will be less than $10, less than $70, and $1200, respectively, in high volume for end of calendar 2001.

About Xilinx

Xilinx is the leading supplier of complete programmable logic solutions, including advanced integrated circuits, software design tools, predefined system functions delivered as cores, and unparalleled field engineering support. Founded in 1984 and headquarters in San Jose, Calif., Xilinx invented field programmable gate arrays (FPGA) and fulfills more than half of the world demand for these devices today. Xilinx solutions enable customers to significantly reduce the time required to develop products for the computer, peripheral, telecommunication, networking, industrial control, instrumentation, aerospace, defense, and consumer markets. For more information, visit the Xilinx web site at www.xilinx.com.