Exemplar Logic Interface: Glossary
Behavioral Simulation
Also known as functional simulation. This type of simulation takes place during the
pre-synthesis stage of HDL design. The purpose of this
simulation is to check that the HDL code describes the
desired design behavior.
Bottom-up Design
HDL methodology where already defined HDL blocks are merged into one overall desired design
behavior.
Carry-logic
An architecture feature of the Xilinx Virtex, Spartan, XC4000, and XC5200 families.
Carry-logic was designed to speed-up and reduce the area of counters, adders,
incrementers, decrementers, comparators, and subtractors. Exemplar can synthesize
carry-logic directly.
Cross-probing
Interprocess communication between Exemplar's Schematic viewer, HDL/file editor, and
information message window, that allows users to select instances or signals in one window
and see the corresponding information in the other window. An example is to select a flop
in the schematic viewer, then to goto the HDL and the corresponding HDL code that created
the flop will be highlighted.
- Electronic Design Interchange Format. An industry-standard netlist format.
HDL
- Hardware Description Language. A language which describes circuits in textual code. The
two most widely accepted HDLs are VHDL and Verilog.
IEEE (pronounced "I
triple-E")
- Institute of Electrical and Electronics Engineers.
LogiBLOX
- The M1 incarnation of Blocks of Logic Optimized for Xilinx, a module-synthesis tool that
allows generation of architecture-optimized functions such as counters, adders, and data
registers.
ModelSim
- Model Technology's upcoming VHDL/Verilog simulator,
consolidating MTI's V-System and Mentor Graphics' QuickHDL
simulators.
OSC4
- OSC4 is the name of the synthesis and simulation component that synthesizes and
simulates the XC4000 oscillator. The OSC4 can only be simulated using A1.4 and later
versions.
Post-synthesis Simulation
This type of simulation is usually done after the HDL code has been expanded into
gates. Post-synthesis simulation is similar to behavioral simulation since design behavior
is being checked. The difference is that in post-synthesis simulation the synthesis tool's
results are being checked. If post-synthesis and behavioral simulation match, then the HDL
synthesis tool has interpreted the HDL code correctly.
QuickHDL
Mentor's VHDL/Verilog simulator, written
using an API linked to Model Technology's HDL simulation core.
ROC
The ROC cell is a UNISIM simulation model for the A1.4 (and later) XSI VHDL flow. The
ROC cell simulates the toggling of the GSR (Global Set/Reset) net in the XC4000 for both
functional and timing simulation.
ROCBUF
- The ROCBUF cell like the ROC cell simulates the toggling of the GSR net in both
functional and timing simulation. Like ROC, ROCBUF is a UNISIM cell. The ROCBUF is used
when the user wants to control via a testbench the toggling of the GSR, but does not want
to use the GSR for the synthesized design. While the ROCBUF does add a port to the
top-level entity, the Xilinx A1.4 (and later) implementation tools will not add this port
to the implemented FPGA design. The ROCBUF is a simulation only cell. Use the -gp switch
with NGD2VHDL to add this port to the backend simulation model.
SIMPRIM
All devices supported in the M1 back-annotated simulation flow are simulated with a
common simulation library, which is composed of components known as SIMPRIM's.
Collectively, these common simulation library components are known as the SIMPRIM library.
STARTBUF
The STARTBUF simulates the behavior of the STARTUP device in the XC4000 family.
Instantiation of the STARTBUF is the new means of telling the M1 core tools that the user
wants to manually control the GSR/GTS net via an external pin, or internal source. Use of
the STARTBUF will let the user simulate the behavior of the STARTUP symbol in both
functional and timing simulation.
Timing Simulation
Also known as backannotated timing simulation. This type of simulation takes place
after the HDL design has been synthesized and placed &
routed. The purpose of this simulation is check that the dynamic timing behavior of the HDL design in the target technology.
TOC
The TOC cell is a UNISIM simulation model for the
A1.4 (and later) XSI VHDL flow. The TOC cell simulates the toggling of the GTS (Global
Tri-state) net in the XC4000 for both functional and timing simulation.
TOCBUF
The TOCBUF cell like the TOC cell simulates the toggling
of the GTS net in both functional and timing simulation. Like TOC, TOCBUF is a UNISIM cell. The TOCBUF is used when the user wants to
control via a testbench the toggling of the GTS, but does not want to use the GTS for the
synthesized design. While the TOCBUF does add a port to the top-level entity, the Xilinx
A1.4 implementation tools will not add this port to the implemented FPGA design. The
TOCBUF is a simulation only cell. To replace this port in the back-end simulation model,
use the -tp switch when invoking NGD2VHDL.
Top-down Design
HDL methodology where overall design behavior is defined
first, and then HDL blocks.
Unisim
- A VHDL/Verilog-based
library that allows behavioral simulation of instantiated Unified-library components in QuickHDL or ModelSim.
Verilog
- An industry-standard HDL developed by Cadence Design Systems. Recognizable as a
file with a .v extension.
VHDL
- VHSIC Hardware Description Language. An
industry-standard (IEEE 1076.1) HDL.
Recognizable as a file with a .vhd or .vhdl extension.
VHSIC
- Very High Speed Integrated Circuit.
VITAL
- VHDL Initiative Toward ASIC Libraries. A VHDL-library
standard (IEEE 1076.4) that defines standard constructs
for simulation modeling, accelerating and improving the performance of VHDL simulators.
X-BLOX
Blocks of Logic Optimized for Xilinx. A schematic-based synthesis tool where generic
bus-width-independent symbols such as counters, adders, and data registers are used to
implement architecture-optimized functions. XBLOX has been replaced in the M1 release with
LogiBLOX.
XNF
- Xilinx Netlist Format.
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