Within one year of launching the original Virtex series, Xilinx has raised the bar yet again by introducing the next generation 1.8-volt Virtex-E family that enhances all aspects of the Virtex attributes. Fabricated on a leading edge 0.18 um, six-layer metal silicon process, the Virtex-E family has significantly increased both performance and density, while providing a high-performance system level feature set that further addresses the bandwidth requirements of the next generation data communication and DSP applications. The advanced high-performance feature set of the Virtex series includes: Densities ranging from 50,000 to 3.2 million system gates  Support for 20 I/O standards, including three differential signaling standards  Over 311 Mbps single-ended I/O performance  622 Mbps differential I/O performance  Up to 832 Kbits of internal True Dual-Port(TM) BlockRAM  8 DLLs for 311+ MHz clock management  Up to 804 single-ended I/Os or 344 differential I/O pairs  Direct interfacing to high performance memory devices  A complete package offering including high pin count, high thermal dissipation, and low-cost package Since it is fully supported by Xilinx(TM) Alliance Series(TM) and Foundation Series(TM) software, as well as all of the EDA tools from Xilinx Alliance partners, the Virtex series is a complete solution ready to meet the challenges of next generation designs. The available software also includes the built-in CORE Generator(TM) tool with a variety of web downloadable Smart-IP(TM) BaseBlox(TM) cores. The Virtex solution helps system designers quickly create very complex designs with guaranteed results.  The First FPGA Solution to Deliver Over 100 Gigabits Per Second (Gbps) I/O Bandwidth  With the growth of the Internet fueling the need for higher data transfer rate, system designers are constantly challenged to maximize the bandwidth of their data communication systems. Bandwidth is a key differentiator for many end products. The fact that computing architectures are now measured in million of instructions per second (MIPS) and data communication systems are measured in gigabits per second (Gbps) further underscores the importance of bandwidth. The Virtex-E family couples advanced DLLs with high-performance SelectI/O+(TM) and SelectLink(TM) technologies that deliver I/O performance at over 311 Megabits per second (Mbps). This enables Virtex-E family to support high performance systems that require bandwidth of over 100 Gbps. SelectI/O+ Technology 20 single-ended and differential signaling standards are supported by all I/Os Up to 344 pairs of differential I/O pairs supporting LVPECL, Bus LVDS, and LVDS Up to 804 single-ended I/Os at over 311 Mbps each  622 Mbps LVDS and LVPECL performance  Simultaneous support of multiple voltages by all I/Os (1.8, 2.5, 3.3, and 5*** volts SelectLink Technology Double-Data Rate (DDR) Virtex-E to Virtex-E link Bandwidth of 300+ Mbps per pin 19.2 Gbps with 64-bit data-path using SSTL2 Built-in FIFOs and flow-control Web-based HDL generation methodology User enters internal and external bus-widths, FIFO resources, and I/O standard selection HDL (Verilog/VHDL) modules generated in second   Table 1. I/O Standards Supported by Virtex-E Family Standard Typical Application LVTTL 3.3 V General Purpose LVCMOS2 2.5 V General Purpose  LVCMOS18** 1.8 V General Purpose  PCI33_5*   33/66 MHz 5 V PCI Backplane PCI33_3, PCI66_3 33/66 MHz 3.3 V PCI Backplane SSTL2 (I,II), SSTL3(I,II), CTT SDRAM, DDR SRAM HSTL(I,III,IV) SRAM, DDR SDRAM, Backplanes GTL, GTL+, AGP Backplanes, Microprocessor Interfacing  LVDS** Point-to-Point Backplanes, High Noise Immunity  BLVDS**  Bus LVDS Backplanes, High Noise Immunity, Bus Architecture Backplanes  LVPECL**  High Performance Clocking, Backplanes, Differential 100MHz+ Clocking, Optical Transceiver, High Speed Networking, and Mixed-Signal Interfacing  5 V TTL***( 4mA Iol )  Legacy 5V TTL Interfacing

* Supported by Virtex family only ** Supported by Virtex-E family only  *** Requires 100 Ohm external resistor for Virtex-E family The First FPGA Solution To Deliver Complete High-Performance Differential Signaling Support As the need for higher bandwidth continues to accelerate, system designers are turning to differential signaling as the mechanism of choice to satisfy high bandwidth requirements while reducing power, increasing noise immunity, and decreasing EMI emissions. The Virtex-E family delivers the industry's highest bandwidth and the most flexible differential signaling solution. The selectI/O+ technology offers direct interfacing to Low Voltage Positive Emitter Coupled Logic (LVPECL), Low Voltage Differential Signaling (LVDS), and Bus LVDS (BLVDS) differential I/O standards. The Virtex-E family offers a hierarchy of differential support, including up to 36 pairs for LVDS and LVPECL at 622 Mbps, and up to 344 differential pairs at over 311 Mbps. High performance and flexibility of the differential solution enables the Virtex-E family to provide multiple 10 Gbps ports while maintaining high signal integrity. Unlike other PLD solutions, all Virtex-E differential I/Os support input, output, and I/O signaling, providing system designers with the unparalleled flexibility to create interfaces to industry standard differential signaling devices. In addition, Virtex-E BLVDS capability can also support multiple configurations including standard Point-to-Point, Multi-Point data distribution and Multi-Drop bus configurations. This feature allows designers to customize their high-performance backplane applications while maximizing overall bandwidth.

Table 2. Virtex-E Family LVDS and BLVDS Support

Direct interface to:



- 133 MHz SDRAM 


- 200 MHz ZBT SRAM


- 266 MHz DDR SDRAM


- Future QDR SRAM  

 

The Virtex Series Solution:  Leading-Edge Software and Intellectual Property (IP) Support  The Virtex architecture was designed in conjunction with our synthesis partners in order to assure maximum performance, predictability, and simplified integration of intellectual property. The Xilinx solution includes:  Complete Virtex series support in Alliance Series and Foundation Series software, both of which feature powerful implementation tools to maximize performance while enhancing productivity  Optimized place and route algorithms that provide a 50% reduction in compile time as compared to the previous software release  Team-based design environment, through Xilinx Internet Team Design (Xilinx iTD(TM)) tool,that increases productivity for multi-module designs  Support for third party signal analysis tools which ensures clean signal integrity (Alliance Series only)  Smart-IP technology and CORE Generator tools that enable high design productivity  BaseBlox cores that have been highly optimized for performance and utilization  The Real-PCI(TM) 64/66 and 32/33 LogiCORE(TM) solutions that are fully PCI compliant  A variety of AllianceCORE(TM) products which span a breadth of applications in communications, networking, video and image processing, computing, and other market segments  Summary  The revolutionary 2.5-volt Virtex family of FPGAs broke new density and performance barriers by expanding the traditional usage of the programmable logic, delivering the first FPGA platform that truly addressed system-level design challenges. With the introduction of the next generation 1.8-volt Virtex-E family, Xilinx has taken FPGA performance to the next level, thereby providing a compelling alternative to ASIC solutions. Virtex series consists of two high-performance FPGA families that range in density from 50,000 to 3,200,000 system gates with up to 622 Mbps I/O performance. The Virtex series features advanced DLLs for high-performance clock management, a hierarchy of memory resources, and I/Os capable of simultaneously interfacing to twenty voltages and signaling standards. The Virtex series solution combines maximum I/O and memory bandwidths with leading-edge software and IP support in order to deliver a solution that best addresses the bandwidth, cost and time-to-market challenges of the next generation data communication and DSP applications.