Hardware Implementation

The Industry's Most Advanced Implementation Tools, Foundation Series ISE also includes Xilinx' latest implementation tools, seamlessly integrated to help you create the most efficient and compact designs that operate at the highest possible speed.

After you have synthesized your VHDL files, you will have a top level EDIF file (as well as sub level EDIF files) in your synthesis project. This are the EDIF files that you will use as input source for the Xilinx Design Manager.

Foundation ISE include the following features:

• Timing Driven Place and Route - Allows you to specify your timing requirements for critical paths. This feature often gives 30-40% performance improvements when speed is critical; you no longer need to manually fine-tune your design.
• Static Timing Analysis - Shortens your design process by providing an evaluation of your timing at various points in the implementation process, allowing you to make changes immediately.
• Simulation - Provides design verification before and after implementation, thus reducing the number of design iterations required to meet design specifications.
• Incremental Design Capability - Reduces your overall design cycle by allowing you to re-use previous iterations of your design. This is very helpful for evaluating design alterations.
• Hierarchical Timing Analysis - The Interactive Timing Analyzer organizes and displays data that allows you to analyze the critical paths in your circuit, the cycle time of the circuit, the delay along any specified paths, and the paths with the greatest delay. It also provides a quick analysis of the effect of different speed grades on the same design.
• Integrated Logic Analysis - Xilinx has created the industries best Integrated Logic Analysis tool in order to address the debug verification bottleneck. ChipScope ILA is a silicon based analysis solution that is included as a core function within your design. ChipScope ILA enables the in-system analysis of any signal that is available within the FPGA, while operating within the target system.

Xilinx Design Manager

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