Step 1 System-Level Design
- The MathWorks MATLAB & Simulink
- Xilinx System Generator
Step 2 HDL Synthesis - Two tools to choose from
- FPGA Advantage from Mentor Graphics
- Synplify Pro from Synplicity
Step 3 Simulation
- ModelSim from Model Technology found within the Mentor Graphics FPGA advantage tool set
- You may repeat step 3 for simulation with timing values after running Step 4 place and route.
Step 4 Hardware Implementation
- Xilinx Foundation ISE Software
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