 |
 |
Xilinx creates the highest performing DSP
platforms by exploiting the parallelism that is inherent in the DSP
mathematical models. The vast logic resources in Xilinx Virtex-II
devices—densities up to 8 million system gates and up to 3 million
bits of block RAM—enable you to create fully parallel structures when
you need the greatest possible computational power and bandwidth.
You gain the performance advantage of an ASIC without the added expense
of inflexibility, long lead-times, and hefty non-recurring engineering
(NRE) costs.
|
 |
|
The Virtex-II architecture provides the Xilinx exclusive Active
Interconnect ™Technology, featuring actively driven segmented routing
between each building block element on the FPGA. When combined with
unique Xilinx Smart-IP™ Technology, these features ensure that performance
is consistent over the entire range of FPGA device sizes, independently
of the surrounding user-logic and level of integration. Up to 168
18x18-bit high-performance combinatorial multipliers embedded in silicon
support data rates up to 200 MHz. These allow for fast and efficient
implementations of adaptive filters, equalizers and FFTs used in applications
such as xDSL and cable modems or Gigabit Ethernet.
Distributed DSP Resources
- Xilinx FPGA fabric is an array of lookup tables (LUTs), registers,
memory, and multipliers
- Supports up to 8 million system gates, enabling super high-performance
DSP functions through tremendous parallel processing
Data Storage
- Up to 3 Mbit of True Dual-Port™ Block RAM allows for single-chip
implementation of large FFTs, video line buffers, and other memory
intensive DSP functions
- Up to 1.9 Mbit of distributed memory for storage of coefficients
and data
- Can be configured as RAM/ROM/FIFO or shift registers
Arithmetic Functions
- Up to 168 18x18 embedded multipliers enabled optimal implementation
of high-speed non-pipelined DSP functions
- Distributed arithmetic multipliers constructed from lookup tables
(LUT) provide efficient pipelined data structures
- Fast carry chains for addition and subtraction carry look-ahead
arithmetic pipelining enable signals to be pipelined either through
registers or memory
System
Features
- Xilinx Platform FPGA solution provides complete system features
such as microprocessors, high-speed I/Os and DDLs allow for complete
system integration - including DSP, memory interfaces, and control
logic
- Up to 420 MHz system clock rates
- 840 Mbps differential I/O performance
- 420 MHz - Clock synthesis / Phase manipulation
|
|
![[Xilinx_Inc.]](../images/xtremedsp.gif)
