Xilinx Design Reuse

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Xilinx Design Reuse Overview

The need for design reuse has been apparent for many years; no company likes to put many man years of effort into a design that can be used only once. Today, thousands of designers are creating intellectual property (IP) on a huge scale, targeting the widely popular million-gate Virtex!" FPGA family which is ideally suited to support design reuse.

This web site has been created to meet this fast growing demand for reusable IP and IP management tools. Xilinx is addressing some of these Design Reuse issues with a new tool, the
IP Internet Capture which works in conjunction with the Xilinx CORE Generator System.

Also available is design reuse documentation in the form of the Xilinx FPGA Reuse Field Guide, and the Xilinx Design Reuse Methodology (HDL coding style guide).

The intent of these tools and manual is to help design teams implement designs for reuse and share their intellectual property internally and over the web.