![](../../../../bvdocs/images/dot_clear.gif) |
|
The Xilinx and ARC Cores Alliance for Configurable Processor Cores on Xilinx
FPGAs
|
![ARC logo](ARC.gif) |
![](../../../../images/xilinx.gif) |
Overview
|
Xilinx and ARC Cores have teamed up to offer the ARC soft 32-bit configurable
processor solution for use in Virtex
and Spartan ® series FPGAs.
Xilinx customers now have access to a high-performance, user-configurable
32-bit processor, or can purchase customized Xilinx versions for specific
applications from a growing network of world-wide design
centers. |
|
The ARC is a user customizable 32-bit microprocessor architecture that
has a variety of advantages over conventional approaches. The ARC is a
powerful and flexible processor that provides the optimal design solution
for embedded processor based applications. The ARC architecture can be
configured to meet specific performance and cost targets. This makes it
suitable for a wider range of applications than would an external or embedded
fixed instruction set processor. The ARC tool set allows a designer to
customize the processor to achieve either greater system performance or
lower power at reduced clock frequencies, making it ideal as a soft, FPGA-based
solution. |
![ARC System Block Diagram](arcblock.gif) |
ARC System Block Diagram
|
|
For example, a voice codec for a GSM-based wireless communications
system requires a clock speed of at least 115 MHz on a fixed instruction-set
processor, to be compliant with GSM standards. A Virtex-based
ARC core, configured to include specific instructions for the codec algorithm,
is fully compliant at well below 1 MHz. Other Virtex
FPGA-based ARC solutions have been proven for DSP, Voice over IP (VoIP),
and MP3 applications. |
The ARC 32-bit configurable processor is available now for use in Xilinx
programmable logic devices. Datasheets and information are available in
the Xilinx-IP Center. For more information about
ARC Cores and their products, you can submit
a request, or visit their home page. |
![ipcenter logo](../../../../images/ipcenter_logo.gif) |
![AllianceCORE Logo](../../../../images/ac_logo.gif) |
ARC Cores is a member of the AllianceCORE
program, a cooperative effort between Xilinx and independent third-party
core developers. It is designed to produce a broad selection of industry-standard
solutions dedicated for use in Xilinx programmable logic. |
|
|
ARC Angel Hardware Development System
|
ARC Cores provides the ARCangel
II hardware development system that includes a Virtex
XCV1000-6 FPGA. The board allows ACDC members and fully-licensed users
to configure, test and iterate their ARC-based designs in a Virtex
FPGA prior to committing their systems to board-level design. The reconfigurable
nature of both the ARC processor and the Xilinx FPGA delivers unlimited
flexibility for optimization. |
![ARC Angel Development System](arcangel.jpg) |
![Virtex Logo](../../../../images/svirtex.gif) |
![Spartan Logo](../../../../images/spartan3.gif) |
|
|
World-Wide ARC Certified Design Center (ACDC) Network
|
A network of certified design centers will configure, optimize
and integrate the ARC processor for use in Xilinx FPGAs. Qualification
for this program will include joint certification by ARC and Xilinx of
consulting firms who will receive ARC Certified Design Center (ACDC) and
Xilinx XPERTS‘ third-party consultant
training. Resulting ACDC companies firms will be able to deliver optimized
Xilinx netlist implementations of pre-configured ARC processors. The charter
members of this network are listed below, and more will be added over time. |
![Fraunhofer Logo](iis250.gif) |
Fraunhofer Institut Integrierte Schaltungen
Am Weichselgarten 3
D-91058 Erlangen
Germany
Phone: +49 (0) 91 31/7 76-4 37
FAX: +49 (0) 91 31/7 76-4 99
URL: www.iss.fhg.de |
![DELTA Logo](delta.gif) |
DELTA - Danish Electronics, Light and Accoustics
Venlighedsvej 4
DK-2970 Horsholm
Denmark
Phone: +45 45 86 77 22
Fax: +45 45 86 58 98
URL: www.delta.dk |
|
|
Datasheet and Additional Information
to view the
.PDF files below |
|
|