Instructions
The circuit shown below can be used to deskew a system clock between
a Spartan-II chip and other non-Spartan-II chips on the same board.
This application is commonly used when the Spartan-II device is
used in conjunction with other standard products such as SRAM or
DRAM devices. While designing the board level route, ensure that
the return net delay to the source equals the delay to the other
chips involved. Do not use the DLL output clock signals until after
activation of the LOCKED signal. Prior to the activation of the
LOCKED signal, the DLL output clocks are not valid and can exhibit
glitches, spikes, or other spurious movement.
VHDL
-- Requires external connection
of CLK0_ext to CLKFB on the board.
--
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity dll_mirror_1 is
port (CLKIN : in std_logic;
CLKFB : in std_logic;
CLK0_ext : out std_logic;
CLK0_int : out std_logic);
end dll_mirror_1;
architecture structural of dll_mirror_1 is
signal CLKIN_w, CLKFB_w, CLK0_int_dll, CLK0_int_g, CLK0_ext_dll :
std_logic;
signal logic0 : std_logic;
begin
logic0 <= '0';
clkpad : IBUFG port map (I=>CLKIN, O=>CLKIN_w);
clkfbpad : IBUFG port map (I=>CLKFB, O=>CLKFB_w);
dllint : CLKDLL port map (CLKIN=>CLKIN_w, CLKFB=>CLK0_int_g, RST=>logic0,
CLK0=>CLK0_int_dll, CLK90=>open, CLK180=>open, CLK270=>open, CLK2X=>open,
CLKDV=>open, LOCKED=>open);
dllext : CLKDLL port map (CLKIN=>CLKIN_w, CLKFB=>CLKFB_w, RST=>logic0,
CLK0=>CLK0_ext_dll, CLK90=>open, CLK180=>open, CLK270=>open, CLK2X=>open,
CLKDV=>open, LOCKED=>open);
clkg : BUFG port map (I=>CLK0_int_dll, O=>CLK0_int_g);
clkextpad : OBUF port map (I=>CLK0_ext_dll, O=>CLK0_ext);
CLK0_int <= CLK0_int_g;
end structural;
Verilog
// Requires external connection
of CLK0_ext to CLKFB on // the board.
//
module dll_mirror_1 (CLKIN, CLKFB, CLK0_ext, CLK0_int);
input CLKIN, CLKFB;
output CLK0_ext, CLK0_int;
wire CLKIN_w, CLKFB_w, CLK0_int_dll, CLK0_ext_dll;
wire logic0;
assign logic0 = 1'b0;
IBUFG clkpad (.I(CLKIN), .O(CLKIN_w));
IBUFG clkfbpad (.I(CLKFB), .O(CLKFB_w));
CLKDLL dllint (.CLKIN(CLKIN_w), .CLKFB(CLK0_int), .RST(logic0), .CLK0(CLK0_int_dll),
.CLK90(), .CLK180(), .CLK270(), .CLK2X(), .CLKDV(), .LOCKED());
CLKDLL dllext (.CLKIN(CLKIN_w), .CLKFB(CLKFB_w), .RST(logic0), .CLK0(CLK0_ext_dll),
.CLK90(), .CLK180(), .CLK270(), .CLK2X(), .CLKDV(), .LOCKED());
BUFG clkg (.I(CLK0_int_dll), .O(CLK0_int));
OBUF clkextpad (.I(CLK0_ext_dll), .O(CLK0_ext));
endmodule |
