Instructions
The circuit shown below can be used to deskew a system clock between
multiple Spartan-II chips on the same board. While designing the
board level route, ensure that the return net delay to the source
equals the delay to the other chips involved. Do not use the DLL
output clock signals until after activation of the LOCKED signal.
Prior to the activation of the LOCKED signal, the DLL output clocks
are not valid and can exhibit glitches, spikes, or other spurious
movement.
VHDL
-- Requires external connection
of CLK0_ext to CLKFB on the board.
--
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity dll_mirror_2 is
port (CLKIN : in std_logic;
CLKFB : in std_logic;
CLK0_ext : out std_logic;
CLK0_int : out std_logic;
NOT_LOCKED : out std_logic);
end DLL_mirror_2;
architecture structural of DLL_mirror_2 is
signal CLKIN_w, CLKFB_w, CLK0_int_DLL, CLK0_int_g, CLK0_ext_DLL :
std_logic;
signal LOCKED_ext_DLL, NOT_LOCKED_w : std_logic;
signal logic0 : std_logic;
begin
logic0 <= '0';
clkpad : IBUFG port map (I=>CLKIN, O=>CLKIN_w);
clkfbpad : IBUFG port map (I=>CLKFB, O=>CLKFB_w);
dllint : CLKDLL port map (CLKIN=>CLKIN_w, CLKFB=>CLK0_int_g, RST=>logic0,
CLK0=>CLK0_int_DLL, CLK90=>open, CLK180=>open, CLK270=>open, CLK2X=>open,
CLKDV=>open, LOCKED=>open);
dllext : CLKDLL port map (CLKIN=>CLKIN_w, CLKFB=>CLKFB_w, RST=>logic0,
CLK0=>CLK0_ext_DLL, CLK90=>open, CLK180=>open, CLK270=>open, CLK2X=>open,
CLKDV=>open, LOCKED=>LOCKED_ext_DLL);
clkg : BUFG port map (I=>CLK0_int_DLL, O=>CLK0_int_g);
clkextpad : OBUF port map (I=>CLK0_ext_DLL, O=>CLK0_ext);
CLK0_int <= CLK0_int_g;
NOT_LOCKED_w <= not LOCKED_ext_DLL;
notlckpad : OBUF port map (I=>NOT_LOCKED_w, O=>NOT_LOCKED);
end structural;
Verilog
// Requires external connection
of CLK0_ext to CLKFB on the board.
//
module DLL_mirror_2 (CLKIN, CLKFB, CLK0_ext, CLK0_int, NOT_LOCKED);
input CLKIN, CLKFB;
output CLK0_ext, CLK0_int, NOT_LOCKED;
wire CLKIN_w, CLKFB_w, CLK0_int_DLL, CLK0_ext_DLL;
wire LOCKED_ext_DLL, NOT_LOCKED_w;
wire logic0;
assign logic0 = 1'b0;
IBUFG clkpad (.I(CLKIN), .O(CLKIN_w));
IBUFG clkfbpad (.I(CLKFB), .O(CLKFB_w));
CLKDLL dllint (.CLKIN(CLKIN_w), .CLKFB(CLK0_int), .RST(logic0),
.CLK0(CLK0_int_DLL), .CLK90(), .CLK180(), .CLK270(),
.CLK2X(), .CLKDV(), .LOCKED());
CLKDLL dllext (.CLKIN(CLKIN_w), .CLKFB(CLKFB_w), .RST(logic0),
.CLK0(CLK0_ext_DLL), .CLK90(), .CLK180(), .CLK270(),
.CLK2X(), .CLKDV(), .LOCKED(LOCKED_ext_DLL));
BUFG clkg (.I(CLK0_int_DLL), .O(CLK0_int));
OBUF clkextpad (.I(CLK0_ext_DLL), .O(CLK0_ext));
assign NOT_LOCKED_w = ! LOCKED_ext_DLL;
OBUF notlckpad (.I(NOT_LOCKED_w), .O(NOT_LOCKED));
endmodule
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