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Virtex-E High
Performance Differential Solution: Low Voltage Differential
Signaling (LVDS)
As the need for higher bandwidth accelerates, system designers
are turning to differential signaling as the mechanism of choice
to satisfy high bandwidth requirements while reducing power,
increasing noise immunity, and decreasing EMI emissions. LVDS
is a low swing, differential signaling technology providing
very fast data transmission, common-mode noise rejection, and
low power consumption over a broad frequency range. The Virtex-E
family delivers the programmable industry's highest bandwidth
and most flexible differential signaling solution for direct
interfacing to industry standard LVDS devices. With up to 36
I/O pairs operating at 622 Megabits per second (Mbps) or up
to 344 I/O pairs operating at over 311 Mbps, the Virtex-E family
supports multiple 10 Gigabit per second (Gbps) ports while maintaining
high signal integrity with low power consumption. Unlike other
PLD solutions, all Virtex-E LVDS I/Os support input, output,
and I/O signaling, providing system designers the unparalleled
flexibility in board layout. Table 1 summarizes the LVDS support
in the Virtex-E family.
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For more technical details including the graphics and waveforms, click
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LVDS Configuration |
Bandwidth | Point
to Point | 36 pairs @ 622 Mbps or 344
pairs @ 311 Mbps | Multi-Drop |
344 pairs @ 311 Mbps | Table
1: Virtex-E High-Bandwidth LVDS Support Summary |
The LVDS Standard
LVDS is defined by two industry
standards: ANSI/TIA/EIA-644 and IEEE 1596.3 SCI-LVDS standards. - The
ANSI/TIA/EIA-644 standard defines LVDS electrical specs including driver output
and receiver input electrical characteristics. It does not cover functional specifications,
protocols, or transmission medium characteristics since these are application
dependent. The ANSI/TIA/EIA-644 is the more generic of the two standards and is
intended for multiple applications.
- The IEEE 1596.3 SCI-LVDS standard
is a subset of SCI (Scalable Coherent Interface). The SCI-LVDS standard defines
electrical specifications for the physical layer interface of SCI. The SCI-LVDS
standard is similar to the ANSI/TIA/EIA-644 standard but differs in the intended
usage of the interface. The IEEE committee created the SCI-LVDS standard for communication
between SCI nodes.
The Virtex-E LVDS solution conforms to the ANSI/TIA/EIA-644
standard. Table 2 summarizes the pertinent Virtex-E LVDS DC specifications (source:
Virtex-E Data Sheet) DC
Parameter | Conditions | Min | Typ | Max | Units | VCCO | | 2.375 | 2.5 | 2.625 | V | Output
High Voltage for Q and QB | RT
= 100 Ohms across Q and QB signals | 1.25 | 1.425 | 1.6 | V | Output
Low Voltage for Q and QB | RT
= 100 Ohms across Q and QB signals | 0.9 | 1.075 | 1.25 | V | Differential
Output Voltage (Q - QB), Q= High(Q-QB), QB = High | RT
= 100 Ohms across Q and QB signals | 250 | 350 | 450 | mV | Output
Common-Mode Voltage | RT
= 100 Ohms across Q and QB signals | 1.125 | 1.25 | 1.375 | V | Differential
Input Voltage (Q - QB), Q= High(Q-QB), QB = High | Common-mode
input voltage = 1.25 V | 100 | 350 | NA | mV | Input
Common-Mode Voltage | Differential input voltage
= +-350 mV | 0.2 | 1.25 | 2.2 | V |
Table
2: Virtex-E LVDS DC Specifications |
Advantages
- LVDS is specified to be technology and process independent.
- LVDS
is EMI tolerant. Common-mode noise is equally removed by two conductors and rejected
by the receiver.
- No transmission medium is defined in the standard. The
medium can be tailored to meet the specific application requirements. ·
- The
typical LVDS voltage swing is 350 mV, resulting in a higher transfer rate and
lower power consumption.
Configurations
There are two configurations that are used in the LVDS applications,
point-to-point and multi-drop. The Virtex-E family supports both LVDS configurations.
Point-to-Point In point-to-point configuration,
there is one transmitter and one receiver. The LVDS driver is a current source
that drives a differential pair of lines. The typical current drive is 3.5 mA.
The receiver has high DC impedance. The majority of the driver current flows across
the termination resistor generating about 350 mV at the receiver inputs. Multi-Drop A
multi-drop LVDS configuration has one transmitter and multiple receivers. The
differential termination resistor is placed close to the last receiver.
Applications
Applications for LVDS include: - Switches
- Repeaters
- Hubs
- Routers
- Wireless base stations
- Flat panel
display
- Digital cameras
- Printers
- Copiers
- Multimedia
peripherals
- Proprietary backplane applications
Termination
LVDS is widely used for high-speed point-to-point interface as well as
multi-drop applications. Depending on the exact interconnect topology, precision
resistors are required to match specific impedance characteristics to minimize
reflection and ensure high signal integrity. The Virtex-E family supports the
most flexible LVDS high-speed interface by supporting flexible external termination
scheme. This enables system designers to customize the resistor value most appropriate
to achieve maximum performance.
Point-to-Point
Figure 1(click here to view Figure 1
in PDF file) shows the schematic of a standard LVDS driver driving the Virtex-E
receiver. An LVDS driver on the left drives the two 50 ohm transmission lines
into a Virtex-E LVDS receiver on the right. The two 50 ohm single-ended transmission
lines can be microstrip, stripline, a 100 ohm differential twisted pair, or a
similar balanced differential transmission line. Figure 2 (click here
to view Figure 2 in PDF file) shows the complete schematic of the Virtex-E LVDS
line driver and receiver. The standard LVDS 100 ohm termination resistor is connected
across the LVDS_OUT and LVDS_OUT' outputs at the end of the transmission line.
Resistors Rs and Rdiv attenuate signals from the Virtex-E LVDS drivers and provide
a matched source impedance (series termination) to the transmission lines. Standard
termination packs are available from Bourns
and other resistor vendors to provide termination networks with up to 16 pins
per pack. Virtex-E LVDS driver meets all ANSI/TIA/EIA-644 LVDS DC specifications.
The matched source impedance of the Virtex-E LVDS driver absorbs nearly all differential
reflections from the capacitive load at the LVDS destination, which reduces standing
waves, undershoot, and signal swing reduction on data bursts or clocks. Data
and clocks can be transmitted over cables longer than 5 ns electrical length,
limited only by the quality of the cable, namely the cable attenuation caused
by skin effect losses at high frequencies. The 622 Mbps data rate, or 311
MHz clock is achievable with the -7 Virtex-E speed grade device. See "XAPP233:
LVDS Transceivers at 622 Mbps using General-Purpose I/O" for details of the
reference design.
Multi-Drop
Multi-drop
LVDS configuration allows many receivers to be driven by one Virtex-E LVDS driver.
With simple source and differential termination, Virtex-E LVDS driver can drive
lines with fan-outs of 20 to 1, making Virtex-E LVDS I/Os suitable for a broad
variety of high-load applications. Figure 3 (click here
to view Figure 3 in PDF file) show the complete schematic of the Virtex-E LVDS
driver driving 20 LVDS receivers in a multi-drop configuration. The receivers
can be either Virtex-E receivers or other off-the-shelf LVDS receivers. The LVDS
signal is driven from a Virtex-E LVDS driver on the left, and is daisy-chained
with two 29-ohm transmission lines and stubs to all 20 LVDS receivers. Each LVDS
receiver taps off the main multi-drop lines every 2.5" for a multi-drop line
length of 50". Each LVDS receiver tap line has 1" maximum stub length
with a 50 ohm transmission line impedance to ground, or a differential impedance
of 100 ohms between the two stubs. A 44 ohm termination resistor Rt is placed
across the differential lines close to the last LVDS receiver, on the right. Resistors
RS and Rdiv attenuate the signals from the Virtex-E drivers and provide a 22 ohm
source impedance (series termination) to the 29 ohm transmission lines. The 22
ohm source impedance is used because the added load of the LVDS receivers brings
the 29 ohm line down to an effective average impedance of 22 ohm. The capacitor
Cslew reduces the slew rate from the Virtex-E LVDS driver, resulting in smaller
reflections and less ringing at the receivers. The two 29 ohm single-ended
transmission lines can be microstrip, stripline, the single-ended equivalent of
a 58 ohm twisted pair, or a similar balanced differential transmission line. The
resistors RS and Rdiv should be placed close to the Virtex-E driver outputs. The
parallel termination resistor Rt should be placed close to the final LVDS receiver
inputs at the far end of the multi-drop line. The capacitor Cslew should be placed
close to the resistors RS and Rdiv. Virtex-E multi-drop LVDS driver adheres
to all the ANSI/TIA/EIA-644 LVDS standard DC input level specifications, and is
fully compatible with LVDS receivers from National Semiconductor and other companies.
The maximum data rate is 311 Mbps or a clock of 155.5 MHz for the -7 Virtex-E
speed grade device. Reliable data transmission is possible for up to 20 LVDS receivers
over a multi-drop line length of 50 inches, limited only by skin effect losses
in the PCB trace.
Virtex Advantages
The Virtex-E devices are the first
programmable logic devices available in the market incorporating advanced LVDS
I/O capability with support for other differential standards (Bus LVDS and LVPECL).
Unlike other announced architectures (for example, APEX E), the Virtex-E LVDS
capability provides an abundance of LVDS capable user I/O and clock pins, and
the architectural flexibility as shown in Table 3 to address true high-speed system
issues. This capability works in concert with a robust delay locked loop (DLL)
technology enabling designers to achieve maximum performance in their LVDS applications.
Feature |
Virtex-E |
APEX E
|
Offer LVDS as a standard feature |
Yes, on all devices, packages, and speeds |
Large "x" device only , fast speed only (More $$) |
LVDS | Y |
Y | Bus LVDS |
Y | N |
LVPECL | Y |
N | LVDS Configurations |
Point-to-Point, Multi-Drop, Multi-Point |
Point-to-Point, Multi-Drop* | Max.
I/O Bandwidth | 22 Gbps (=622 Mbps/pr x
36 pairs) or 107 Gbps (= 311 Mbps/pr x 344 pairs) | 10
Gbps (= 622 Mbps/pr x 16 pairs) | Termination |
External, Flexible | Internal
on outputs, inflexible | # High-speed Differential
Clk Pairs | 4 |
1 | Max. # of differential
pairs | 344 In/Out |
Dedicated 16 input and 16 output (Not layout friendly) |
Max. Speed | 622 Mbps |
622 Mbps | Serializer/deserializer |
Flexible in CLB | Dedicated
8:1 | Clock recovery | N |
N | Note: *
APEX E has internal termination on the outputs, and cannot guarantee high signal
integrity due to inability to do impedance matching
Table
3: Virtex-E versus APEX E LVDS Solution |
Unlike
other PLD solution that only offers LVDS capability in the most expensive and
highest speed grade options, the Virtex-E DLL and LVDS I/O capabilities are standard
features available in all Virtex-E device/package combinations. Virtex-E family
offers users the option to use up to 36 LVDS I/O pairs operating at 622 Mbps or
up to 344 LVDS I/O pairs operating at over 311 Mbps to achieve over 100 Gbps aggregate
bandwidth. This enables system designers to support multiple 10 Gbps ports architecture
for today's high-performance DSP and data communication systems. Table 4 below
demonstrates the high-bandwidth LVDS solution provided by the Virtex-E family.
In addition to offering a high-performance and highly flexible LVDS solution,
Xilinx also works closely with other component vendors (ex. Bourns
for the resistor pack) to ensure interoperability and help system designers further
reduce the overall design complexity and system cost.
Number of I/O |
I/O Standard |
Type | 1 |
2 | 32 |
72 | 688 |
Virtex-E LVDS |
Differential | NA |
622 Mbps | 10
Gbps | 22 Gbps |
107 Gbps | APEX-E
LVDS | Differential |
NA | 622 Mbps |
10 Gbps | NA |
NA | Table
4: Virtex-E High-Bandwidth LVDS Solution Summary |
References
Standards
Standards ANSI/TIA/EIA-644
IEEE
1596.3 Related
Xilinx Documents
to view the
PDF files below.
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