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What's New
Success Stories
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The XC9500XL CPLD family is targeted for leading-edge systems that require rapid design development, longer system life, and robust field upgrade capability. This 3.3V in-system programmable family provides unparalleled performance and the highest programming reliability, with the lowest cost in the industry. The XC9500XL CPLDs also complement the higher density Xilinx FPGAs to provide a total logic solution, within a unified development environment. The XC9500XL family is fully WebPOWERED via its free WebFITTER and WebPACK™ ISE™ software.
| Family Highlights |
- Lowest cost per macrocell
- State-of-the-art pin-locking architecture
- Highest programming reliability reduces system risk
- Complements Xilinx 3.3V FPGA families
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Features
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Benefits
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- Highest performance 5ns/222Mhz
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- Leading-edge computing application
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- Most flexible pin-locking architecture
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- Design iterations without board rework
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- Highest device reliability
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- Higher quality, reduced support cost
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- Reduced board area, increased flexibility
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- In-system programming via JTAG
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- Compatible with industry-standard ISP
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- Robust 5V, 3.3V, 2.5V interfacing
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- Worry-free mixed voltage operation
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- Easily accessible and free software tools saves development time and cost
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Unprecedented Performance
- 5 ns pin-to-pin speed
- 222 MHz system frequency
Powerful Architecture
- Wide 54-input function blocks
- Up to 90 product-terms per macrocell
- Fast and routable FastCONNECT II switch matrix
- Three global clocks with local inversion
- Individual OE per output, with local inversion
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Highest Reliability
- Endurance rating of 10,000 cycles
- Data retention rating of 20 years
- Immune from "ISP Lock-Out" failure mode
- Allows arbitrary mixed-power sequencing and waveforms
Advanced Technology
- 3rd generation, proven CPLD technology
- Mainstream, scalable, high-reliability processing
- Fast in-system programming and erase times
Outperforms All Other 3.3V CPLDs
- Extended data retention supports longer system operating life
- Virtually eliminates in-system programming failures
- Superior pin-locking for lower design risk
- Glitch-free I/O pins during power-up
- Full IEEE 1149.1 (JTAG) ISP and boundary-scan test
- Free WebPOWERED software
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XC9536XL
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XC9572XL
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XC95144XL
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XC95288XL
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| Macrocells |
36
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72
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144
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288
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| Usable Gates |
800
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1,600
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3,200
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6,400
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| Registers |
36
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72
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144
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288
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| tPD (ns) |
5
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5
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5
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6
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| fSYSTEM (MHz) |
222
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222
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222
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208
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| User I/O Pins |
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44-pin PLCC
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34
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34
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44-pinVQFP
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34
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34
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64-pin VQFP
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36
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52
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100-pin TQFP
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72
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81
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144-pin TQFP
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117
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117
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208-pin PQFP
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168
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48-pin CSP
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36
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38
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144-pin CSP
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117
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256-pin BGA
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192
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256-pin FBGA
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192
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280-pin CSP
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192
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