Axcelerator RAM

Features

• Parameterized word length and depth

• Dual-port synchronous RAM architecture

• Independent Read/Write sizes

• Active High/Low enable

• Active High/Low Read and Write clocks

• Non-pipelined (synchronous - one clock edge)/ Pipelined (synchronous - two clock edges) Read

• Port mapping

• Memory Editor

Family Support

Axcelerator

Description

Axcelerator provides dedicated blocks of RAM. Each block has a read port and a write port. Both ports are configurable to any size from 4Kx1 to 128x36; thereby, allowing built-in bus width conversion (see SRAM Port Aspect Ratio table below). Each port is completely independent and fully synchronous.

Modes

The three major modes available for read and write operations are:

• Read Non-pipelined (synchronous - one clock edge)
  The read address is registered on the read port clock edge and data appears at read-data after the RAM access time (when all RENs are high, approximately 4.5ns). The setup time of the read address and read enable are minimal with respect to the read clock. Setting the Pipeline to OFF enables this mode.

• Read Pipelined (synchronous - two clock edges)
  The read-address is registered on the read port clock edge and the data is registered and appears at read-data after the second read clock edge. Setting the Pipeline to ON enables this mode.

• Write (synchronous - one clock edge)
  On the write clock edge, the write data are written into the USRAM at the write address (when all WENs are high). The setup time of the write address, write enables and write data are minimal with respect to the read clock.

Cascading Blocks

Blocks can be cascaded to create larger sizes. SmartGen performs all the necessary cascading for achieving the desired configuration. To achieve good performance, all cascaded RAM blocks must fit within one RAM column of the selected device. Cascading RAM blocks deep is possible only up to the capacity of one RAM column.

However, if the specified configuration exceeds one RAM column, SmartGen tries to cascade the RAM wide, up to the available RAM Blocks in the device. This will result in poorer performance as the RAM blocks are not physically close to one another.

The maximum WIDTH (word length) value is 65,536. The maximum DEPTH (number of words) value is 576.

The Read/Write Width/Depth can be different but the aspect ratio should be same for both. For example:

Read Width * Read Depth == Write Width * Write Depth

The write enable (WE) and read enable (RE) signals are active high or low request signals for writing and reading, respectively; you may choose not to use them. When none is selected for an enable, that operation remains enabled all the time.

For example, if WEN is chosen as none, then write operation of the RAM is enabled all the time.

The RCLK and WCLK pins have independent polarity selection.

Conflict Resolution

There is no special hardware for handling read and write operations at the same addresses.