ProASIC3E RAM512x18

ProASIC3E has two memory elements: RAM4K9 and RAM512x18.

Features

RAM512x18 is a two port RAM and supports the following features.

• Variable aspect ratios of 512x9 or 256x18

• Dedicated Read and Write Ports

• Active Low Read and Write Enable

• Synchronous Write and Pipelined or Non-Pipelined Synchronous Read

• Active Low Asynchronous Output Reset

Description

RAM512X18 has dedicated Read and Write Ports.

WW and RW

These signals enable the RAM to be configured into one of the two allowable aspect ratios.

WD and RD

These are the input data and output signals and are 18 bits wide. When 512X9 aspect ratio is used for Write, WD[17:9] are unused and must be grounded. If this aspect ratio is used for Read, then RD[17:9] is undefined.

WADDR and RADDR

These are read and write addresses and are 9 bits wide. When 256X18 aspect ratio is used for Write or Read, WADDR[8] or RADDR[8] is unused and must be grounded

WCLK and RCLK

These signals are the write and read clocks respectively. They are both Active High.

WEN and REN

These signals are the write and read enables respectively. They are both Active Low.

RESET

This Active Low signal resets the output to zero when asserted. It does not reset the contents of the memory.

PIPE

This signal is used to specify pipelined read on the output. A Low on the PIPE indicates a non-pipelined read and the data appears on the output in the same clock cycle. A High indicates a pipelined read and data appears on the output in the next clock cycle.

RAM512X18 Truth Table