Creating your testbench with WaveFormer Lite

WaveFormer Lite generates VHDL and Verilog testbenches from drawn waveforms. Create your testbench after you are done creating your design and wish to perform simulation.

There are five basic steps for creating testbenches using WaveFormer Lite and Libero IDE. These steps are described in detail in the following sections.

To create a testbench using WaveFormer Lite:

1. Click WaveFormer Lite in the Design Flow Window. WaveFormer Lite starts and your signal information is imported automatically .  

2. Using WaveFormer Lite, draw the waveforms to describe the testbench.

3. From the Export menu, choose Export Timing Diagram and choose the save type as *.tim or *.btim. This saves the waveforms.  

4. (Optional) Add VHDL Libraries and Use Clauses for VHDL export. These libraries or packages can be included using the VHDL Libraries and Use Clauses dialog. From the Options menu, select the VHDL Libraries and Use Clauses menu item to open this dialog.

5. From the Export menu, choose Export Timing Diagram and choose the type of file to generate. You can generate a testbench with a top-level module that automatically hooks up the model under test to the testbench, or you can generate just a testbench model. Below is a detailed description of the two methods:

• To generate a Top-Level Model and a Testbench model choose one of the "top-level" scripts from the save as type drop-down list box. The top-level module instantiates the model under test and hooks it up to the testbench. For this script to work the top-level module needs to be defined in the project. For WaveFormer Lite customers, the Actel Software should automatically set this option. Below is a list of top-level scripts:

• VHDL Wait with Top Level Testbench (*.vhd)s

• VHDL Transport with Top Level Testbench (*.vhd)s

• Verilog with Top Level TestBench (*.v)s

• To generate a plain testbench model (which does not instantiate your model under test), choose one of the VHDL or Verilog scripts. To simulate with the testbench model, you will need to write a top-level model that instantiates the testbench model and the model under test. This is the method used by Wave-Former Pro customers. Below is a list of VHDL and Verilog testbench generation scripts:

• VHDL Wait (*.vhd)s

• VHDL Transport (*.vhd)s

• Verilog

5. From the File menu, choose Exit.
    

Note: If you added extra signals to the testbench and do not want to export those signals, then double-click the signal’s names to open the Signals Properties dialog and clear the Export check box.

Synplify always changes the data type to std_logic or std_logic_vector in the post_synthesis netlist. If your top-level entity port is not std_logic or std_logic_vector and you need to run post-synthesis or post-layout simulation, you need to change the data type in WFL.  

To create two testbenches:

1. Open the .tim file and select the special data type signal, right-click and choose Edit Selected Signal.

2. Choose std_logic or std_logic_vector under VHDL and click Save.

If you are running pre-synthesis simulation you do not need to change the data type in WFL.