The following table shows which families support this constraint and which file formats and tools you can use to enter or modify it:
Families |
PDC |
GCF |
ChipPlanner |
Fusion |
X |
|
|
ProASIC3E |
X |
|
|
ProASIC3 |
X |
|
|
ProASIC PLUS |
|
X |
X |
Axcelerator |
X |
|
|
ProASIC |
|
X |
X |
eX |
|
|
|
SX-A |
|
|
|
SX |
|
|
|
MX |
|
|
|
3200DX |
|
|
|
ACT3 |
|
|
|
ACT2/1200XL |
|
|
|
ACT1 |
|
|
|
Use this constraint to assign regular nets to local clock routing or to LocalClock regions. This results in the creation of a LocalClock region that spans the area of the local clock net.
If there are enough local clock resources but not enough global clock routing resources available in a device, you can assign regular nets that have high fan-out to the dedicated local clock routing resources which can lead to better performance for your design.
You can use one or more of the following commands or GUI tools to assign a net to a local clock:
PDC - assign_local_clock
GCF - use_global
ChipPlanner - Creating LocalClock regions