The following table shows which families support this constraint and which file formats and tools you can use to enter or modify it:
|
Families |
PDC |
ChipPlanner |
|
Fusion |
X |
X |
|
ProASIC3E |
X |
X |
|
ProASIC3 |
X |
X |
|
ProASIC PLUS |
|
|
|
Axcelerator |
X |
X |
|
ProASIC |
|
|
|
eX |
|
|
|
SX-A |
|
|
|
SX |
|
|
|
MX |
|
|
|
3200DX |
|
|
|
ACT3 |
|
|
|
ACT2/1200XL |
|
|
|
ACT1 |
|
|
Use this constraint to allow the software to choose the default VREF pin for I/O banks.
For voltage-referenced I/Os, each bank also has a common reference-voltage bus, VREF. You can enable the software to configure a default set of pins to be VREFs. These pins will then be used by other I/Os in that bank for reference voltage.
You can use one or more of the following commands or GUI tools to configure default pins as VREFs:
PDC - set_vref_defaults
ChipPlanner - Assigning VREF_pins