Set false path

• Families supported

• Purpose

• Tools / How to enter

Families Supported

The following table shows which families support this constraint and which file formats and tools you can use to enter or modify it:

(*) Supported for analysis only.

(**) Supported for layout only.

(***) Only the -through option is supported for layout.

Purpose

Use this constraint to identify paths in the design that should be disregarded during timing analysis and timing optimization.    

By definition, false paths are paths that cannot be sensitized under any input vector pair. Therefore, including false paths in timing calculation may lead to unrealistic results. For accurate static timing analysis, it is important to identify the false paths.

You can set false paths constraints in an SDC file, which you can either create yourself or generate with Synthesis tools, at the same time you import the netlist. Alternatively, you can set false paths using the GUI tools in the Designer software when you implement your design.

Tools /How to Enter

You can use one or more of the following commands or GUI tools to set false paths:

• SDC - set_false_path

• GCF - set_false_path (backwards compatible for ProASIC families only)

• DCF - global_stops

• Timer - Breaks tab

• SmartTime - Specifying false path constraint

See Also

Constraint entry

set_false_path (SDC)

set_false_path (GCF)

global_stops (DCF)

Breaks tab

Specifying false path constraint