When you create a new project in the Libero IDE it automatically creates new directories and project files. Your project directory contains all of your 'local' project files. If you import files from outside your current project, the files must be copied into your local project folder. (Libero IDE enables you to manage your files as you import them.)
Depending on your project preferences and the version of Libero IDE you installed, Libero IDE creates SmartGen, constraint, designer,hdl, package, phy_synthesis, simulation, stimulus, synthesis, and viewdraw directories for your project.
The toplevel directory (<project_name>) contains your PRJ file; only one PRJ file is enabled for each Libero IDE project.
smartgen directory - GEN files and LOG files from generated SmartGen cores
constraint directory - All your constraint files (SDC, PDC, GCF, DCF, etc.)
designer directory - ADB files (Actel Designer project files), -_ba.SDF, _ba.v(hd), STP, PRB (for Silicon Explorer), TCL (used to run designer), impl.prj_des (local project file relative to revision), designer.log (logfile)
Note: The Actel ADB file memory requirement is equivalent to 2x the size of the ADB file. If your computer does not have 2x the size of your ADB file's memory available, please make memory available on your hard drive.
hdl directory - all hdl sources. *.vhd if VHDL, *.v and *.h if Verilog
package directory - VHD files
phy_synthesis directory - _palace.edn, _palace.gcf, palace_top.rpt (palace logfile) and other files generated by PALACE
simulation directory - meminit.dat, modelsim.ini files
stimulus directory - BTIM and VHD stimulus files
synthesis directory - *.edn, *_syn.prj (Synplify log file), *.psp (Precision project file), *.srr (Synplify logfile), precision.log (Precision logfile), exemplar.log (Leonardo logfile), *.tcl (used to run synthesis) and many other files generated by the tools (not managed by Libero IDE)
viewdraw directory - viewdraw.ini