Use Logic regions to compact the placement of certain logic blocks in your design. This allows you to control logic placement at the region or block level. This may simplify your floorplanning task, since you might not have to place logic instances individually on the device. The following sections contain guidelines for using Logic regions.
If you partitioned your design into several modules, and some of these modules contain regular structures (such as arithmetic logic, register arrays, counters, or multiplexors), place these modules into Logic regions. These logic functions have a good amount of both local connectivity and regularity to their structure, which makes them good candidates for regions. Interconnects between your regions now become interconnects between hierarchical blocks in your design. Floorplan your regions so there is a smooth horizontal or vertical data flow between each Logic region.
If you assigned logic to a region so its inputs and outputs are bounded by a register array (pipeline registers), it is a good idea to place these pipeline registers close to the boundary of the region. If you plan to manually fix the placement of your pipeline registers, make sure you orient them in the correct direction to assure a smooth data flow between them and their interfacing logic.
Before placing your memory blocks, review your design and understand how data is flowing into and out of them. Determine what logic blocks are driving the memory inputs (for example, address line, control signals) and what logic is driven by the memory outputs (for example, databus lines). Follow these guidelines:
Place pins that drive or are driven by your memory blocks close to where your memory blocks are placed.
Create an empty region next to your memory block to free up local routing resources that may need to be used to connect to the memory blocks.
If you are driving high fan-in memory inputs such as read/write clocks or read/write enables, try using low-skew routing resources such as global nets or clock spines to connect them. Make sure your clock spine assignments are aligned with your RAM placement.