set_multitile_location (ProASIC3/E)

Assigns specified two-tile and four-tile macros to specified locations on the chip. Use this command only for multi-tile, flip-flop macros and, in some cases, enable flip-flop macros).

set_multitile_location macro_name [-fixed value]\

  -location {x y} \

  -tile {name1 relative_x1 relative_y1} \

  -tile {name2 relative_x2 relative_y2} \

  [-tile {name3 relative_x3 relative_y3} \ ]

  [-tile {name4 relative_x4 relative_y4} \ ]

Arguments

macro_name

Specifies the hierarchical name of the macro in the netlist to assign to a particular location on the chip.

-fixed value

Sets whether the location of this set of macros is fixed (that is, locked). Locked macros are not moved during layout. The default is yes.  The following table shows the acceptable values for this argument:

-location {x y}

The x and y coordinates specify the absolute placement of the macro on the chip. You can use the ChipPlanner tool to determine the x and y coordinates of the location.

-tile {name1 relative_x1 relative_y1}

Specifies the hierarchical name and location, relative to the macro specified as the macro_name, of the first tile in a two- or four-tile macro. The relative placement of macro name1 inside the macro cannot be offset by more than one. (See Notes below for placement rules.) If the macro uses four-tile macros, then you must define all four tiles. Likewise, if the macro uses two-tile macros, you must define both tiles.

You can place the following two-tile and four-tile macros with the set_multitile_location command:

Due to the ProASIC3/E architecture, if the CLR and PRE pins are NOT driven by a clock net (global, quadrant or local clock net), the enable flip-flop macros (shown below) are mapped to two-tile flip-flop macros. When CLR and PRE pins are not driven by a clock net, you must use the set_multitile_location command instead of the set_location command.

During compile, Designer maps the specified enable flip-flop macro to a two-tiled macro.

If the CLR and PRE pins are driven by a clock net, Designer maps these macros to one tile during compile. In this case, you cannot use the set_multitile_location command to place them. Instead, you must use the set_location command.

Supported Families

Fusion and ProASIC3/E

Description

For two-tile flip-flop macros, the software appends U0 and U1 to the macro name. For four-tile flip-flop macros, the software appends U0, U1, U2 and U3 to the macro name. The macros specified in the -tile option cannot be offset by more than one.

To ensure efficiency, you must use local connections between certain tiles in the macros. The distance between U0 and U1, U1 and U2, and U2 and U3 must not be more than one in either direction (X or Y). The required local connection between tiles is denoted by the dashes below:

Four-tile macros:    U0 --- U1 --- U2 --- U3
Two-tile macros:    U0 --- U1

Examples of possible placement configurations:

Exceptions

• None

Examples

This example assigns and locks the macro with instance name “multi_tileff/U0 “ at the location X=10, Y=10 by specifying the relative positions of all the macros.

set_multitile_location multi_tileff -location {10 10} \

                       -tile { multi_tileff/U0 0 0 } \

                       -tile { multi_tileff/U1 0 1 } \

                       -tile { multi_tileff/U2 0 2 } \

                       -tile { multi_tileff/U3 0 3 } -fixed yes

As a result of this command, the four-tile macro placement looks like this:

The second example shows you how to configure a two-tile macro:

set_multitile_location multi_tileff -location {10 10} \

                       -tile { multi_tileff/U0 0 0 } \

                       -tile { multi_tileff/U1 1 0 }

As a result of this command, the two-tile macro placement looks like this:

See Also

Assign macro to location

set_location

PDC syntax conventions

PDC naming conventions