About ChipPlanner in MultiView Navigator

ChipPlanner is the floorplanning tool you use to create and edit regions on your chip and assign logic to these regions. You can also use it to view routing information and influence place and route for more optimal results. This tool is particularly useful when you need maximum control over your design placement.

Note:  ChipPlanner supports only the Fusion, ProASIC3E, ProASIC3, ProASIC PLUS, Axcelerator, ProASIC. SX-A, and eX families. If you are designing for other families, use  ChipEditor.

Use ChipPlanner to:

• View macro assignments made during layout

• Assign, unassign, or move macros

• Lock macro assignments

• View net connections using a ratsnest or route view

• View architectural boundaries

• View and edit silicon features, such as I/O banks

• Create regions and assign macros or nets to regions (floorplanning)

• View placement and routing of paths when used with SmartTime

Using PDC Files (Fusion, ProASIC3E, ProASIC3, and Axcelerator only)

Any constraint that you can enter using ChipPlanner, you can also enter using a Physical Design Constraint (PDC) file. A PDC file is a Tool Command Language (Tcl) script file specifying physical constraints. This file can be imported and exported from Designer. PDC files replace the PIN file for the Axcelerator family.

Using GCF Files (ProASIC and ProASIC PLUS only)

Any constraint that you can enter using ChipPlanner, you can also enter using a GCF file. A GCF file is a constraint file specifying placement or timing constraints. This file can be imported and exported from Designer.  

See Also

Overview (MultiView Navigator)

Starting ChipPlanner