The steps for performing functional and timing simulation are nearly identical. Functional simulation is performed before place-and-route and simulates only the functionality of the logic in the design. Timing simulation is performed after the design has gone through place-and-route and uses timing information based on the delays in the placed and routed designs.
Timing simulation includes much more detailed timing information for the targeted device. Timing simulation requires a testbench.
To perform timing simulation:
If you have not done so, back-annotate your design and create your testbench.
Right-click the top level module in the Design Hierarchy Menu and choose Organize Stimulus File from the right-click menu.
In the Organize Stimulus dialog box, all the stimulus files in the current Libero project appear in the left Stimulus Files in the Project list box. Files already associated with the block appear in the Associated Files list box.
In most cases, you will only have one testbench associated with your block. However, if you want simultaneous association of multiple testbench files for one simulation session, as in the case of PCI cores, add multiple files to the Associated Files dialog box.
To add a testbench: Select the testbench you want to associate with the block in the Stimulus Files in the Project list box and click Add to add it to the Associated Files list.
To remove a testbench: To remove or change the file(s) in the Associated Files list box, select the file(s) and click Remove.
To order testbenches: Use the up and down arrows to define the order you want the testbenches compiled.
When you are satisfied with the Associated File(s) list, click OK. A check mark appears next to WaveFormer Lite in the Design Flow window to let you know that a testbench has been associated with the block.
Click ModelSim Simulation in the Design Flow window. The ModelSim simulator starts and compiles the source files. When the compilation completes, the simulator runs for 1 mS and a Wave window opens to display the simulation results.
Scroll in the Wave window to verify the logic works as intended. Use the cursor and zoom buttons to zoom in and out and measure timing delays. If you did not create a testbench with WaveFormer Lite, you may get error messages with the vsim command if the instance names of your testbench do not follow the same conventions as WaveFormer Lite. Ignore the error message and type and the correct vsim command.
When you are done, from the File menu, choose Quit.