set_input_delay (SDC)

Defines the arrival time of an input relative to a clock.

set_input_delay delay_value -clock clock_ref [–max] [–min] [–clock_fall] input_list

Arguments

delay_value

Specifies the arrival time in nanoseconds that represents the amount of time for which the signal is available at the specified input after a clock edge.

-clock clock_ref

Specifies the clock reference to which the specified input delay is related. This is a mandatory argument. If you do not specify -max or -min options, the tool assumes the maximum and minimum input delays to be equal.

-max

Specifies that delay_value refers to the longest path arriving at the specified input. If you do not specify -max or -min options, the tool assumes maximum and minimum input delays to be equal.

-min

Specifies that delay_value refers to the shortest path arriving at the specified input. If you do not specify -max or -min options, the tool assumes maximum and minimum input delays to be equal.

-clock_fall

Specifies that the delay is relative to the falling edge of the clock reference. The default is the rising edge.

input_list

Provides a list of input ports in the current design to which delay_value is assigned. If you need to specify more than one object, enclose the objects in braces ({}).

Supported Families

Fusion, ProASIC3/E, ProASICPLUS, Axcelerator, ProASIC (for analysis), eX (for analysis), SX-A (for analysis)

Description

The set_input_delay command sets input path delays on input ports relative to a clock edge. This usually represents a combinational path delay from the clock pin of a register external to the current design. For in/out (bidirectional) ports, you can specify the path delays for both input and output modes. The tool adds input delay to path delay for paths starting at primary inputs.

A clock is a singleton that represents the name of a defined clock constraint. This can be:

a single port name used as source for a clock constraint
a single pin name used as source for a clock constraint; for instance reg1:CLK. This name can be hierarchical (for instance toplevel/block1/reg2:CLK)
an object accessor that will refer to one clock: [get_clocks {clk}]

Examples

The following example sets an input delay of 1.2ns for port data1 relative to the rising edge of CLK1:

set_input_delay 1.2 -clock [get_clocks CLK1] [get_ports data1]

The following example sets a different maximum and minimum input delay for port IN1 relative to the falling edge of CLK2:

set_input_delay 1.0 -clock_fall -clock CLK2 –min {IN1}

set_input_delay 1.4 -clock_fall -clock CLK2 –max {IN1}

Actel Implementation Specifics