set_output_delay (SDC)

Defines the output delay of an output relative to a clock.

set_output_delay delay_value -clock clock_ref [–max] [–min] [–clock_fall] output_list

Arguments

delay_value

Specifies the amount of time before a clock edge for which the signal is required. This represents a combinational path delay to a register outside the current design plus the library setup time (for maximum output delay) or hold time (for minimum output delay).

-clock clock_ref

Specifies the clock reference to which the specified output delay is related. This is a mandatory argument. If you do not specify -max or -min options, the tool assumes the maximum and minimum input delays to be equal.

-max

Specifies that delay_value refers to the longest path from the specified output. If you do not specify -max or -min options, the tool assumes the maximum and minimum output delays to be equal.

-min

Specifies that delay_value refers to the shortest path from the specified output. If you do not specify -max or -min options, the tool assumes the maximum and minimum output delays to be equal.

-clock_fall

Specifies that the delay is relative to the falling edge of the clock reference. The default is the rising edge.

output_list

Provides a list of output ports in the current design to which delay_value is assigned. If you need to specify more than one object, enclose the objects in braces ({}).

Supported Families

Fusion, ProASIC3/E, ProASICPLUS, Axcelerator, ProASIC (for analysis), eX (for analysis), SX-A (for analysis)

Description

The set_output_delay command sets output path delays on output ports relative to a clock edge. Output ports have no output delay unless you specify it. For in/out (bidirectional) ports, you can specify the path delays for both input and output modes. The tool adds output delay to path delay for paths ending at primary outputs.

Examples

The following example sets an output delay of 1.2ns for port OUT1 relative to the rising edge of CLK1:

set_output_delay 1.2 -clock [get_clocks CLK1] [get_ports OUT1]

The following example sets a different maximum and minimum output delay for port OUT1 relative to the falling edge of CLK2:

set_output_delay 1.0 -clock_fall -clock CLK2 –min {OUT1}

set_output_delay 1.4 -clock_fall -clock CLK2 –max {OUT1}

Actel implementation specifics