Specifying clock constraints is the most effective way of constraining and verifying the timing behavior of a sequential design. You must use clock constraints to meet your performance goals and to quickly reach timing closure.
Actel recommends that you specify and constrain all clocks used in the design.
To create a clock constraint, you must provide the following clock information:
Clock source: Specifies the pin or port where the clock signal is defined.
Clock period or frequency: Defines the smallest amount of time after which the signal repeats itself.
Duty cycle: Defines the percentage of time during which the clock period is high.
First edge: Indicates whether the first edge of the clock is rising or falling.
Offset: Indicates the shift of the first edge with respect to instant zero common to all clocks in the design.
create_clock -period 10 -waveform {2 7}
This example creates a clock with 10ns period, 2ns offset, and 50% duty cycle using the SDC command.
This example shows how to create a clock with 25MHz frequency, 4ns offset for its first rising edge, and 60% duty cycle using the SmartTime Constraints Editor. Using the Create New Clock Constraint dialog box is equivalent to using the SDC command: create_clock -period 40 -waveform {4, 28}.
