create_clock (SDC)

Creates a clock and defines its characteristics.

create_clock -period period_value [-waveform edge_list] source

Arguments

-period period_value

Specifies the clock period in nanoseconds. The value you specify is the minimum time over which the clock waveform repeats. The period_value must be greater than zero.

-waveform edge_list

Specifies the rise and fall times of the clock waveform in ns over a complete clock period. There must be exactly two transitions in the list, a rising transition followed by a falling transition. You can define a clock starting with a falling edge by providing an edge list where fall time is less than rise time. If you do not specify -waveform option, the tool creates a default waveform, with a rising edge at instant 0.0ns and a falling edge at instant (period_value/2)ns.

source

Specifies the source of the clock constraint. The source can be ports or pins in the design. If you specify a clock constraint on a pin that already has a clock, the new clock replaces the existing one. Only one source is accepted. Wildcards are accepted as long as the resolution shows one port or pin.

Supported Families

Fusion, ProASIC3/E, ProASICPLUS, Axcelerator, ProASIC (for analysis), eX, SX-A

Description

Creates a clock in the current design at the declared source and defines its period and waveform. The static timing analysis tool uses this information to propagate the waveform across the clock network to the clock pins of all sequential elements driven by this clock source.

The clock information is also used to compute the slacks in the specified clock domain that drive optimization tools such as place-and-route.

Exceptions

None

Examples

The following example creates two clocks on ports CK1 and CK2 with a period of 6, a rising edge at 0, and a falling edge at 3:

create_clock -period 6 CK1

create_clock –period 6 –waveform {0 3} {CK2}

The following example creates a clock on port CK3 with a period of 7, a rising edge at 2, and a falling edge at 4:

create_clock –period 7 –waveform {2 4} [get_ports {CK3}]

Actel Implementation Specifics

The -waveform in SDC accepts waveforms with multiple edges within a period. In Actel design implementation, only two waveforms are accepted.
SDC accepts defining a clock on many sources using a single command. In Actel design implementation, only one source is accepted.
The source argument in SDC create_clock command is optional. This is in conjunction with the -name argument in SDC to support the concept of virtual clocks. In Actel implementation, source is a mandatory argument as -name and virtual clocks concept is not supported.
The -domain argument in the SDC create_clock command is not supported.