Use this dialog box to define specific timing paths as being false.
This constraint removes timing requirements on these false paths so that they are not considered during the timing analysis. The path starting points are the input ports or register clock pins and path ending points are the register data pins or output ports. This constraint disables setup and hold checking for the specified paths.
Note: The false path information always takes precedence over multiple cycle path information and overrides maximum delay constraints.
To open the Set False Path Constraint dialog box (shown below) from the SmartTime Constraints Editor, choose Actions > Constraints > False Path.
Set False Path Constraint Dialog Box
Specifies the starting points for false path. A valid timing starting point is a clock, a primary input, an inout port, or a clock pin of a sequential cell.
Specifies a list of pins, ports, cells, or nets through which the disabled paths must pass.
Specifies the ending points for false path. A valid timing ending point is a clock, a primary output, an inout port, or a data pin of a sequential cell.
Enables you to provide comments for this constraint.